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PDF IDT71T024L150PZI Data sheet ( Hoja de datos )
| Número de pieza | IDT71T024L150PZI | |
| Descripción | LOW POWER 2V CMOS SRAM 1 MEG (128K x 8-BIT) | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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Integrated Device Technology, Inc.
LOW POWER 2V CMOS SRAM
1 MEG (128K x 8-BIT)
ADVANCE
INFORMATION
IDT71T024
FEATURES:
• 128K x 8 Organization
• Wide Operating Voltage Range: 1.8V to 2.7V
• Speed Grades: 150ns, 200ns
• Low Operating Power: 11mA (max)
• Low Standby Power: 5µA (max)
• Low-Voltage Data Retention: 1.5V (min)
• Available in 32-pin, 13.4mm x 8mm Type I TSOP pack-
age
DESCRIPTION:
The IDT71T024 is a 1,048,576-bit very low-power Static
RAM organized as 128K x 8. It is fabricated using IDT’s high-
reliability CMOS technology. This state-of-the-art technology,
combined with innovative circuit design techniques, provides
a cost-effective solution for low-power memory needs. It uses
a 6-transistor memory cell.
Operation is from a single extended-range 2.5V supply.
This extended supply range makes the device ideally suited
for unregulated battery-powered applications. Fully static
asynchronous circuitry is used, requiring no clocks or refresh
for operation.
The IDT71T024 is packaged in a JEDEC standard 32-pin
TSOP Type I.
FUNCTIONAL BLOCK DIAGRAM
A0
•
•
•
A16
ADDRESS
DECODER
•
•
•
1,048,576-BIT
MEMORY ARRAY
I/O0 – I/O7
•
8
8
WE
OE
CONTROL
LOGIC
CS1
CS2
I/O CONTROL
8
3779 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
©1997 Integrated Device Technology, Inc.
MAY 1997
DSC-3779/1
1
1 page  
IDT71T024
LOW POWER 2V CMOS STATIC RAM 1 MEG (128K x 8-BIT)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS (VDD = 1.8 to 2.7V, All Temperature Ranges)
71T024L150
Symbol
Parameter
Min. Max.
Read Cycle
tRC Read Cycle Time
150 —
tAA Address Access Time
— 150
tACS
tCLZ(1)
tCHZ(1)
Chip Select Access Time
Chip Select Low to Output in Low-Z
Chip Select High to Output in High-Z
— 150
20 —
— 30
tOE
tOLZ(1)
tOHZ(1)
Output Enable Low to Output Valid
Output Enable Low to Output in Low-Z
Output Enable High to Output in High-Z
— 75
20 —
— 30
tOH Output Hold from Address Change
15 —
Write Cycle
tWC Write Cycle Time
150 —
tAW Address Valid to End of Write
120 —
tCW Chip Select Low to End of Write
120 —
tAS Address Set-up Time
0—
tWR Address Hold from End of Write
0—
tWP Write Pulse Width
100 —
tDW Data Valid to End of Write
60 —
tDH
tOW(1)
tWHZ(1)
Data Hold Time
Write Enable High to Output in Low-Z
Write Enable Low to Output in High-Z
0—
5—
— 40
NOTE:
1. This parameter is guaranteed by device characterization, but is not production tested.
71T024L200
Min. Max. Units
200 — ns
— 200 ns
— 200 ns
20 — ns
— 40 ns
— 100 ns
20 — ns
— 40 ns
15 — ns
200 — ns
160 — ns
160 — ns
0 — ns
0 — ns
140 — ns
80 — ns
0 — ns
5 — ns
— 50 ns
3779 tbl 11
5
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| PDF Descargar | [ Datasheet IDT71T024L150PZI.PDF ] | |
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