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PDF IDT71B74S10TP Data sheet ( Hoja de datos )
| Número de pieza | IDT71B74S10TP | |
| Descripción | BiCMOS STATIC RAM 64K (8K x 8-BIT) CACHE-TAG RAM | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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Integrated Device Technology, Inc.
BiCMOS STATIC RAM
64K (8K x 8-BIT)
CACHE-TAG RAM
IDT71B74
FEATURES:
• High-speed address to MATCH comparison time
— Commercial: 8/10/12/15/20ns (max.)
• High-speed address access time
— Commercial: 8/10/12/15/20ns (max.)
• High-speed chip select access time
— Commercial: 6/7/8/10ns (max.)
• Power-ON Reset Capability
• Low power consumption
— 830mW (typ.) for 12ns parts
— 880mW (typ.) for 10ns parts
— 920mW (typ.) for 8ns parts
• Produced with advanced BiCMOS high-performance
technology
• Input and output directly TTL-compatible
• Standard 28-pin plastic DIP and 28-pin SOJ (300 mil)
DESCRIPTION:
The IDT71B74 is a high-speed cache address comparator
subsystem consisting of a 65,536-bit static RAM organized as
8K x 8 and an 8-bit comparator. A single IDT71B74 can map
8K cache words into a 2 megabyte address space by using the
21 bits of address organized with the 13 LSBs for the cache
address bits and the 8 higher bits for cache data bits. Two
IDT71B74s can be combined to provide 29 bits of address
comparison, etc. The IDT71B74 also provides a single RAM
clear control, which clears all words in the internal RAM to zero
when activated. This allows the tag bits for all locations to be
cleared at power-on or system-reset, a requirement for cache
comparator systems. The IDT71B74 can also be used as a
resettable 8K x 8 high-speed static RAM.
The IDT71B74 is fabricated using IDT’s high-performance,
high-reliability BiCMOS technology. Address access times as
fast as 8ns, chip select times of 6ns and address-to-match
times of 8ns are available.
The MATCH pin of several IDT71B74s can be wired-ORed
together to provide enabling or acknowledging signals to the
data cache or processor, thus eliminating logic delays and
increasing system throughput.
FUNCTIONAL BLOCK DIAGRAM
A0
A12
RESET
I/O0 - 7
8
ADDRESS
DECODER
WE
OE
CS
CONTROL
LOGIC
EQUAL
65,536-BIT
MEMORY ARRAY
I/O CONTROL
VCC
GND
MATCH (OPEN DRAIN)
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc.
14.1
3013 drw 01
AUGUST 1996
DSC-3013/4
1
1 page  
IDT71B74
BiCMOS STATIC RAM 64K (8K x 8-BIT) CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%)
Symbol
Parameter
71B74S8 71B74S10 71B74S12 71B74S15
Min. Max. Min. Max. Min. Max. Min. Max.
Read Cycle
tRC Read Cycle Time
8 — 10 — 12 — 15 —
tAA Address Access Time
— 8 — 10 — 12 — 15
tACS
tCLZ(1)
Chip Select Access Time
Chip Select to Output in Low-Z
— 6 —7 — 8 — 8
2 — 2— 2 — 3 —
tOE
tOLZ(1)
tCHZ(1)
tOHZ(1)
Output Enable to Output Valid
Output Enable to Output in Low-Z
Chip Select to Output in High-Z
Output Disable to Output in High-Z
— 5 —6 — 6 — 8
2 — 2— 2 — 2 —
— 4 —5 — 5 — 7
— 4 —4 — 5 — 5
tOH Output Hold from Address Change 3 — 3 — 3 — 3
NOTE:
1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
—
71B74S20
Min. Max. Unit
20 — ns
— 20 ns
— 10 ns
3 — ns
— 9 ns
2 — ns
— 8 ns
— 8 ns
3 — ns
3013 tbl 10
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
tRC
ADDRESS
tAA
OE
CS
DATAOUT
tOE
tOLZ (5)
tACS (3)
t CLZ (5)
t OH
t OHZ (5)
t CHZ (5)
DATAOUT VALID
TIMING WAVEFORM OF READ CYCLE NO. 2 (1, 2, 4)
tRC
ADDRESS
DATAOUT
tAA
tOH
tOH
DATAOUT VALID
NOTES:
1. WE is HIGH for Read cycle.
2. Device is continuously selected, CS is LOW.
3. Address valid prior to or coincident with CS transition LOW; otherwise tAA is the limiting parameter.
4. OE is continuously active, OE is LOW.
5. Transition is measured ±200mV from steady state.
3013 drw 09
3013 drw 10
14.1 5
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| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet IDT71B74S10TP.PDF ] | |
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