|
|
PDF IDT7143LA70PF Data sheet ( Hoja de datos )
| Número de pieza | IDT7143LA70PF | |
| Descripción | HIGH-SPEED 2K x 16 CMOS DUAL-PORT STATIC RAMS | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de IDT7143LA70PF (archivo pdf) en la parte inferior de esta página. Total 17 Páginas | ||
|
No Preview Available !
Integrated Device Technology, Inc.
HIGH-SPEED
2K x 16 CMOS DUAL-PORT
STATIC RAMS
IDT7133SA/LA
IDT7143SA/LA
FEATURES:
• High-speed access
— Military: 25/35/45/55/70/90ns (max.)
— Commercial: 20/25/35/45/55/70/90ns (max.)
• Low-power operation
— IDT7133/43SA
Active: 500 mW (typ.)
Standby: 5mW (typ.)
— IDT7133/43LA
Active: 500mW (typ.)
Standby: 1mW (typ.)
• Versatile control for write: separate write control for
lower and upper byte of each port
• MASTER IDT7133 easily expands data bus width to 32
bits or more using SLAVE IDT7143
• On-chip port arbitration logic (IDT7133 only)
• BUSY output flag on IDT7133; BUSY input on IDT7143
• Fully asynchronous operation from either port
• Battery backup operation–2V data retention
• TTL-compatible; single 5V (±10%) power supply
• Available in 68-pin ceramic PGA, 68-pin Flatpack, 68-pin
PLCC, and 100-pin TQFP
• Military product compliant to MIL-STD-883, Class B
• Industrial temperature range (–40°C to +85°C) is avail-
able, tested to military electrical specifications
FUNCTIONAL BLOCK DIAGRAM
WR/
(2)
LUB
CEL
DESCRIPTION:
The IDT7133/7143 are high-speed 2K x 16 Dual-Port Static
RAMs. The IDT7133 is designed to be used as a stand-alone
16-bit Dual-Port RAM or as a “MASTER” Dual-Port RAM
together with the IDT7143 “SLAVE” Dual-Port in 32-bit-or-
more word width systems. Using the IDT MASTER/SLAVE
Dual-Port RAM approach in 32-bit-or-wider memory system
applications results in full-speed, error-free operation without
the need for additional discrete logic.
Both devices provide two independent ports with separate
control, address, and I/O pins that permit independent, asyn-
chronous access for reads or writes to any location in
memory. An automatic power down feature, controlled by CE,
permits the on-chip circuitry of each port to enter a very low
standby power mode.
Fabricated using IDT’s CMOS high-performance technol-
ogy, these devices typically operate on only 500mW of power.
Low-power (LA) versions offer battery backup data retention
capability, with each port typically consuming 200µW for a 2V
battery.
The IDT7133/7143 devices have identical pinouts. Each is
packaged in a 68-pin ceramic PGA, a 68-pin flatpack, a 68-pin
PLCC, and a 100-pin TQFP. Military grade product is manu-
factured in compliance with the latest revision of MIL-STD-
883, Class B, making it ideally suited to military temperature
applications demanding the highest level of performance and
reliability.
WR/
(2)
RUB
CER
WR/
(2)
LLB
OEL
WR/
(2)
RLB
OER
I/O8L - I/O15L
I/O0L - I/O7L
BUSYL(1)
A10L
NOTES:
1. IDT7133 (MASTER): BUSY is
open drain output and requires
pull-up resistor of 270Ω.
IDT7143 (SLAVE): BUSY is
input.
2. "LB" designates "Lower Byte"
and "UB" designates "Upper
Byte" for the R/W signals.
A0L
I/O
CONTROL
I/O
CONTROL
ADDRESS
DECODER
11
CEL
MEMORY
ARRAY
ARBITRATION
LOGIC
(IDT7133 ONLY)
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ADDRESS
DECODER
11
CER
©1996 Integrated Device Technology, Inc.
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
6.14
I/O8R - I/O15R
I/O0R - I/O7R
BUSYR(1)
A10R
A0R
2746 drw 01
OCTOBER 1996
DSC-2746/6
1
1 page  
IDT7133SA/LA, IDT7143SA/LA
HIGH-SPEED 2K x 16 DUAL-PORT RAMS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(3) (VCC = 5.0V ± 10%)
Symbol Parameter
ICC Dynamic Operating
Current
(Both Ports Active)
ISB1 Standby Current
(Both Ports — TTL
Level Inputs)
ISB2 Standby Current
(One Port — TTL
Level Inputs)
Test
Condition
CE = VIL
Outputs Open
f = fMAX(4)
CEL and CER = VIH
f = fMAX(4)
CE"A" = VIL and
CE"B" = VIH(5),
f = fMAX(4), Active
Port Outputs Open
Version
MIL. S
L
COM’L. S
L
MIL. S
L
COM’L. S
L
MIL. S
L
COM’L. S
L
IDT7133X20(1)
IDT7143X20(1)
Typ.(2) Max.
––
––
250 310
230 280
––
––
25 80
25 70
––
––
140 200
120 180
IDT7133X25
IDT7143X25
Typ.(2) Max.
250 330
230 300
250 300
230 270
25 90
25 80
25 80
25 70
140 230
100 190
140 200
100 170
IDT7133X35
IDT7143X35
Typ.(2) Max.
240 325
220 295
240 295
210 250
25 75
25 65
25 70
25 60
120 200
100 180
120 180
100 160
Unit
mA
mA
mA
ISB3 Full Standby Current Both Ports CEL & MIL. S –
(Both Ports —
CER > VCC - 0.2V
L–
–
–
CMOS Level Inputs) VIN > VCC - 0.2V or COM’L. S
VIN < 0.2V, f = 0(5)
L
1
0.2
15
5
1 30
0.2 10
1 15
0.2 4
1 30 mA
0.2 10
1 15
0.2 4
ISB4 Full Standby Current CE"A" < 0.2V and MIL. S –
(One Port — All
CE"B" > VCC - 0.2V(6)
CMOS Level Inputs) VIN > VCC - 0.2V or
L–
–
–
VIN < 0.2V
COM’L. S
Active Port Outputs
Open, f = fMAX(4)
L
140
120
190
170
140 220
120 200
140 190
120 170
120 190 mA
100 170
120 170
100 150
NOTES:
2746 tbl 07
1. Commercial only, 0°C to +70°C temperature range.
2. VCC = 5V, TA = +25°C for Typ., and are not production tested. ICCDC = 180mA (Typ.)
3. "X" in part numbers indicates power rating (SA or LA).
4. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions”
of input levels of GND to 3V.
5. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
6. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6.14 5
5 Page 
IDT7133SA/LA, IDT7143SA/LA
HIGH-SPEED 2K x 16 DUAL-PORT RAMS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE(7)
Symbol
Parameter
IDT7133X20(1)
IDT7143X20(1)
Min.
Max.
BUSY TIMING (For MASTER IDT7133)
tBAA
BUSY Access Time from Address
— 20
tBDA
BUSY Disable Time from Address
— 20
tBAC
BUSY Access Time from Chip Enable
—
20
tBDC
tWDD
BUSY Disable Time from Chip Enable
Write Pulse to Data Delay(2)
—
—
17
40
tDDD
tBDD
tAPS
tWH
Write Data Valid to Read Data Delay(2)
BUSY Disable to Valid Data(3)
Arbitration Priority Set Up Time(4)
Write
Hold
After
(6)
BUSY
—
—
5
20
30
25
—
—
BUSY INPUT TIMING (For SLAVE IDT7143)
tWB
tWH
tWDD
tDDD
BUSY Input to Write(5)
Write
Hold
After
(6)
BUSY
Write Pulse to Data Delay(2)
Write Data Valid to Read Data Delay(2)
0
20
—
—
—
—
40
30
IDT7133X25
IDT7143X25
Min.
Max.
— 20
— 20
— 20
— 20
— 50
— 35
— 30
5—
20 —
0—
20 —
— 50
— 35
IDT7133X35
IDT7143X35
Min.
Max.
Unit
— 30 ns
— 30 ns
— 25 ns
— 25 ns
— 60 ns
— 45 ns
— 35 ns
5 — ns
25 — ns
0 — ns
25 — ns
— 60 ns
— 45 ns
2746 tbl 12
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE(7)
Symbol
Parameter
IDT7133X45
IDT7143X45
Min.
Max.
BUSY TIMING (For MASTER IDT7133)
tBAA
BUSY Access Time from Address
— 40
tBDA
BUSY Disable Time from Address
— 40
tBAC
BUSY Access Time from Chip Enable
—
30
tBDC
tWDD
BUSY Disable Time from Chip Enable
Write Pulse to Data Delay(2)
—
—
25
80
tDDD
tBDD
tAPS
tWH
Write Data Valid to Read Data Delay(2)
BUSY Disable to Valid Data(3)
Arbitration Priority Set Up Time(4)
Write
Hold
After
(6)
BUSY
—
—
5
30
55
40
—
—
IDT7133X55
IDT7143X55
Min.
Max.
— 40
— 40
— 35
— 30
— 80
— 55
— 40
5—
30 —
IDT7133X70/90
IDT7143X70/90
Min.
Max.
Unit
—
—
—
—
—
—
—
5/5
30/30
45/45
45/45
35/35
30/30
90/90
70/70
40/40
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
BUSY INPUT TIMING (For SLAVE IDT7143)
tWB BUSY Input to Write(5)
0—
0
— 0/0 — ns
tWH
tWDD
Write
Hold
After
(6)
BUSY
Write Pulse to Data Delay(2)
30 —
30
— 30/30 — ns
— 80
—
80
—
90/90
ns
tDDD
Write Data Valid to Read Data Delay(2)
—
55
—
55
—
70/70
ns
NOTES:
2746 tbl 12
1. 0°C to +70°C temperature range only.
2. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read and Busy".
3. tBDD is calculated parameter and is greater of 0, tWDD - tWP (actual), or tDDD - tDW (actual).
4 To ensure that the earlier of the two ports wins.
5. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
6. To ensure that a write cycle is completed on port "B" after contention on port "A".
7. "X" in part number indicates power rating (SA or LA).
6.14 11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet IDT7143LA70PF.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| IDT7143LA70PF | HIGH-SPEED 2K x 16 CMOS DUAL-PORT STATIC RAMS | Integrated Device Technology |
| IDT7143LA70PFB | HIGH-SPEED 2K x 16 CMOS DUAL-PORT STATIC RAMS | Integrated Device Technology |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |