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PDF IDT7142SA25CB Data sheet ( Hoja de datos )
| Número de pieza | IDT7142SA25CB | |
| Descripción | HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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Integrated Device Technology, Inc.
HIGH-SPEED
2K x 8 DUAL-PORT
STATIC RAM
IDT7132SA/LA
IDT7142SA/LA
FEATURES:
• High-speed access
— Military: 25/35/55/100ns (max.)
— Commercial: 25/35/55/100ns (max.)
— Commercial: 20ns only in PLCC for 7132
• Low-power operation
— IDT7132/42SA
Active: 550mW (typ.)
Standby: 5mW (typ.)
— IDT7132/42LA
Active: 550mW (typ.)
Standby: 1mW (typ.)
• Fully asynchronous operation from either port
• MASTER IDT7132 easily expands data bus width to 16-or-
more bits using SLAVE IDT7142
• On-chip port arbitration logic (IDT7132 only)
• BUSY output flag on IDT7132; BUSY input on IDT7142
• Battery backup operation —2V data retention
• TTL-compatible, single 5V ±10% power supply
• Available in popular hermetic and plastic packages
• Military product compliant to MIL-STD, Class B
• Standard Military Drawing # 5962-87002
• Industrial temperature range (–40°C to +85°C) is available,
tested to miliary electrical specifications
DESCRIPTION:
The IDT7132/IDT7142 are high-speed 2K x 8 Dual-Port
Static RAMs. The IDT7132 is designed to be used as a stand-
alone 8-bit Dual-Port RAM or as a “MASTER” Dual-Port RAM
together with the IDT7142 “SLAVE” Dual-Port in 16-bit-or-
more word width systems. Using the IDT MASTER/SLAVE
Dual-Port RAM approach in 16-or-more-bit memory system
applications results in full-speed, error-free operation without
the need for additional discrete logic.
Both devices provide two independent ports with separate
control, address, and l/O pins that permit independent, asyn-
chronous access for reads or writes to any location in memory.
An automatic power down feature, controlled by CE permits
the on-chip circuitry of each port to enter a very low standby
power mode.
Fabricated using IDT’s CMOS high-performance technol-
ogy, these devices typically operate on only 550mW of power.
Low-power (LA) versions offer battery backup data retention
capability, with each Dual-Port typically consuming 200µW
from a 2V battery.
The IDT7132/7142 devices are packaged in a 48-pin
sidebraze or plastic DIPs, 48-pin LCCs, 52-pin PLCCs, and
48-lead flatpacks. Military grade product is manufactured in
compliance with the latest revision of MIL-STD-883, Class B,
making it ideally suited to military temperature applications
demanding the highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
OEL
WCEL
R/ L
OER
WCER
R/ R
I/O0L- I/O7L
I/O
Control
I/O
Control
BUSYL(1,2)
A10L
A0L
NOTES:
1. IDT7132 (MASTER): BUSY is open
drain output and requires pullup
resistor of 270Ω.
IDT7142 (SLAVE): BUSY is input.
2. Open drain output: requires pullup
resistor of 270Ω.
Address
Decoder
11
CEL
MEMORY
ARRAY
ARBITRATION
LOGIC
11
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
6.02
Address
Decoder
I/O0R-I/O7R
BUSYR (1,2)
A10R
A0R
CER
2692 drw 01
OCTOBER 1996
DSC-2692/8
1
1 page  
IDT7132SA/LA AND IDT7142SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(3)
7132X20(2) 7132X25(5) 7132X35
7142X25(5) 7142X35
7132X55
7142X55
7132X100
7142X100
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Read Cycle
tRC
tAA
tACE
tAOE
tOH
tLZ
tHZ
tPU
tPD
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Output Hold From Address Change
Output Low-Z Time(1,4)
Output High-Z Time(1,4)
Chip Enable to Power Up Time(4)
Chip Disable to Power Down Time(4)
20 —
— 20
— 20
11
3—
0—
— 10
0—
— 20
25 — 35
— 25 —
— 25 —
— 12 —
3—3
0—0
— 10 —
0—0
— 25 —
NOTES:
1. Transition is measured ±500mV from Low or High-impedance voltage Output Test Load (Figure 2).
2. Com'l Only, 0°C to +70°C temperature range. PLCC package only.
3. “X” in part numbers indicates power rating (SA or LA).
4. This parameter is guaranteed by device characterization, but is not production tested.
5. Not available in DIP packages.
— 55
35 —
35 —
20 —
—3
—5
15 —
—0
35 —
— 100 — ns
55 — 100 ns
55 — 100 ns
25 — 40 ns
— 10 — ns
— 5 — ns
25 — 40 ns
— 0 — ns
50 — 50 ns
2689 tbl 08
TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE(1)
tRC
ADDRESS
tAA
tOH
tOH
DATAOUT
BUSYOUT
PREVIOUS DATA VALID
DATA VALID
tBDDH (2,3)
2692 drw 07
NOTES:
1. R/W = VIH, CE = VIL, and is OE = VIL. Address is valid prior to the coincidental with CE transition Low.
2. tBDD delay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read
operations, BUSY has no relationship to valid output data.
3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
6.02 5
5 Page 
IDT7132SA/LA AND IDT7142SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WIDTH EXPANSION WITH BUSY LOGIC
MASTER/SLAVE ARRAYS
When expanding an RAM array in width while using busy
logic, one master part is used to decide which side of the RAM
array will receive a busy indication, and to output that indica-
tion. Any number of slaves to be addressed in the same
address range as the master, use the busy signal as a write
inhibit signal. Thus on the IDT7130/IDT7140 RAM the busy
pin is an output if the part is used as a master (M/S pin = VIH),
and the busy pin is an input if the part used as a slave (M/S pin
= VIL) as shown in Figure 4.
LEFT
R/W
BUSY
R/W
IDT7132
MASTER
BUSY
R/W
BUSY
RIGHT
R/W
BUSY
270 Ω
+5V
270 Ω
+5V
If two or more master parts were used when expanding in
width, a split decision could result with one master indicating
busy on one side of the array and another master indicating
busy on one other side of the array. This would inhibit the write
operations from one port for part of a word and inhibit the write
operations from the other port for the other part of the word.
The busy arbitration, on a master, is based on the chip enable
and address signals only. It ignores whether an access is a
read or write. In a master/slave array, both address and chip
enable must be valid long enough for a busy flag to be output
Wfrom the master before the actual write pulse can be initiated
with either the R/ signal or the byte enables. Failure to
observe this timing can result in a glitched internal write inhibit
signal and corrupted data in the slave.
R/W
IDISDSLTLTA7A71V1V4E4E(212)
R/W
BUSY
BUSY
2692 drw 15
Figure 4. Busy and chip enable routing for both width and depth
expansion with IDT7132 (Master) and IDT7142 (Slave) RAMs.
ORDERING INFORMATION
IDT XXXX
A 999
A
A
Device Type Power Speed Package Process/
Temperature
Range
Blank
B
P
C
J
L48
F
Commercial (0°C to +70°C)
Military (–55°C to +125°C)
Compliant to MIL-STD-883, Class B
48-pin Plastic DIP (P48-1)
48-pin Sidebraze DIP (C48-2)
52-pin PLCC (J52-1)
48-pin LCC (L48-1)
48-pin Ceramic Flatpack (F48-1)
20 Commercial PLCC Only
25
35 Speed in nanoseconds
55
100
LA Low Power
SA Standard Power
7132
7142
16K (2K x 8-Bit) MASTER Dual-Port RAM
16K (2K x 8-Bit) SLAVE Dual-Port RAM
6.02
2692 drw 16
11
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| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet IDT7142SA25CB.PDF ] | |
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