IDT71421SA35TF Datasheet PDF - Integrated Device Technology
| Part Number | IDT71421SA35TF | |
| Description | HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS | |
| Manufacturers | Integrated Device Technology | |
| Logo |  |
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Integrated Device Technology, Inc.
HIGH-SPEED 2K x 8
DUAL-PORT STATIC RAM
WITH INTERRUPTS
IDT71321SA/LA
IDT71421SA/LA
FEATURES:
• High-speed access
—Commercial: 20/25/35/45/55ns (max.)
• Low-power operation
—IDT71321/IDT71421SA
—Active: 550mW (typ.)
—Standby: 5mW (typ.)
—IDT71321/421LA
—Active: 550mW (typ.)
—Standby: 1mW (typ.)
• Two INT flags for port-to-port communications
• MASTER IDT71321 easily expands data bus width to 16-
or-more-bits using SLAVE IDT71421
• On-chip port arbitration logic (IDT71321 only)
• BUSY output flag on IDT71321; BUSY input on IDT71421
• Fully asynchronous operation from either port
• Battery backup operation —2V data retention (LA Only)
• TTL-compatible, single 5V ±10% power supply
• Available in popular hermetic and plastic packages
• Industrial temperature range (–40°C to +85°C) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT71321/IDT71421 are high-speed 2K x 8 Dual-
Port Static RAMs with internal interrupt logic for interproces-
sor communications. The IDT71321 is designed to be used
as a stand-alone 8-bit Dual-Port RAM or as a "MASTER"
Dual-Port RAM together with the IDT71421 "SLAVE" Dual-
Port in 16-bit-or-more word width systems. Using the IDT
MASTER/SLAVE Dual-Port RAM approach in 16-or-more-
bit memory system applications results in full speed, error-
free operation without the need for additional discrete logic.
Both devices provide two independent ports with sepa-
rate control, address, and I/O pins that permit independent,
asynchronous access for reads or writes to any location in
memory. An automatic power down feature, controlled by
CE, permits the on chip circuitry of each port to enter a very
low standby power mode.
Fabricated using IDT's CMOS high-performance technol-
ogy, these devices typically operate on only 550mW of
power. Low-power (LA) versions offer battery backup data
retention capability, with each Dual-Port typically consum-
ing 200µW from a 2V battery.
The IDT71321/IDT71421 devices are packaged in a 52-
pin PLCC, a 64-pin TQFP, and a 64-pin STQFP.
FUNCTIONAL BLOCK DIAGRAM
OEL
WCEL
R/ L
OER
WCER
R/ R
I/O0L- I/O7L
BUSYL(1,2)
A10L
A0L
NOTES:
1. IDT71321 (MASTER): BUSY
is open drain output and
requires pullup resistor of 270Ω.
IDT71421 (SLAVE): BUSY is input.
2. Open drain output: requires pullup
resistor of 270Ω.
(2)
INTL
I/O
Control
I/O
Control
Address
Decoder
CEL
WOEL
R/ L
11
MEMORY
ARRAY
ARBITRATION
and
INTERRUPT
LOGIC
Address
Decoder
11
CER
WOER
R/ R
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc.
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
6.03
I/O0R-I/O7R
BUSYR (1,2)
A10R
A0R
(2)
INTR
2691 drw 01
OCTOBER 1996
DSC-2691/6
1
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IDT71321SA/LA AND IDT71421SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(2)
Symbol
Parameter
71321X20 71321X25 71321X35 71321X55 71321X100
71421X25 71421X35 71421X55 71421X100
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Read Cycle
tRC
tAA
tACE
tAOE
tOH
tLZ
tHZ
tPU
tPD
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Output Hold From Address Change
Output Low-Z Time(1,3)
Output High-Z Time(1,3)
Chip Enable to Power Up Time(3)
Chip Disable to Power Down Time(3)
20 —
— 20
— 20
11
3—
0—
— 10
0—
— 20
25 — 35
— 25 —
— 25 —
— 12 —
3—3
0—0
— 10 —
0—0
— 25 —
NOTES:
1. Transition is measured ±500mV from Low or High-impedance voltage Output Test Load (Figure 2).
2. “X” in part numbers indicates power rating (SA or LA).
3. This parameter is guaranteed by device characterization, but is not production tested.
— 55
35 —
35 —
20 —
—3
—5
15 —
—0
35 —
— 100 — ns
55 — 100 ns
55 — 100 ns
25 — 40 ns
— 10 — ns
— 5 — ns
25 — 40 ns
— 0 — ns
50 — 50 ns
2689 tbl 09
TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE (1)
tRC
ADDRESS
tAA
tOH
tOH
DATAOUT
BUSYOUT
PREVIOUS DATA VALID
DATA VALID
tBDDH (2,3)
2691 drw 06
NOTES:
1. R/W = VIH, CE = VIL, and OE = VIL. Address is valid prior to or coincidental with CE transition Low.
2. tBDD delay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read
operations BUSY has no relationship to valid output data.
3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
6.03 5
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| Information | Total 13 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ IDT71421SA35TF.PDF Datasheet ] | |
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