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PDF IMSA110-G20S Data sheet ( Hoja de datos )
| Número de pieza | IMSA110-G20S | |
| Descripción | IMAGE AND SIGNAL PROCESSING SUB.SYSTEM | |
| Fabricantes | STMicroelectronics | |
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IMSA110
IMAGE AND SIGNAL PROCESSING SUB–SYSTEM
. 1-D/2-D SOFTWARE CONFIGURABLE CON-
VOLVER/FILTER
. ON-CHIP PROGRAMMABLE LINE DELAYS (0
— 1120 STAGES)
. 8-BIT DATA AND 8.5-BIT COEFFICIENT
SLICE
. 21 MULTIPLY-AND-ACCUMULATE STAGES
. 1-D (21) OR 2-D (3 x 7) CONVOLUTION WIN-
DOW
. ON-CHIP POST PROCESSOR FOR DATA
TRANSFORMATION
. FULLY CASCADABLE IN WINDOW SIZE AND
ACCURACY
. 20 MHZ DATA THROUGHPUT (420 MOPS)
. SIGNED/UNSIGNED DATA AND COEFFI-
CIENTS
. MICROPROCESSOR INTERFACE
. HIGH SPEED CMOS IMPLEMENTATION
. TTL COMPATIBLE
. SINGLE +5V ± 10% SUPPLY
. POWER DISSIPATION < 2.0 WATTS
. 100 PIN CERAMIC PGA
PGA100
(Ceramic Grid Array Package)
APPLICATIONS
. 1-D and 2-D digital convolution and correlation
. Real time image processing and enhancement
. Edge and feature detection
. Data transformation and histogram equalisa-
tion
. Computer vision and robotics
. Template matching
. Pulse compression
. 1-D or 2-D interpolation
ORDERING INFORMATION
Part Number
Package
Clock
Speed
IMSA110-G20S PGA100 20MHz
Military/
commercial
commercial
July 1992
1/26
1 page  
Figure 3 : A Typical IMSA110 Based System
General purpose
microprocessor
IMSA110
Input
PSRIN
PSROUT
IMSA110
Cascade
IN
Cascade
OUT
Clock
PSRIN
PSROUT
IMSA110
Cascade
IN
Cascade
OUT
PSRIN
PSROUT
IMSA110
Cascade
IN
Cascade
OUT
Output
3. PROGRAMMABLE SHIFT REGISTERS
The three shift registers are 8 bits wide and are
each programmable from 0 up to 1120 clock cycles
in length. The lengths are programmed into control
registers via the microprocessor interface.
Data is clocked into the device via the PSRin bus
(Programmable Shift Register in) at a maximum
rate of 20MHz. On-chip, the input data is then fed
through a pipeline of the three shift registers. The
output of the first shift register passes to the first
7-stage mac array and also to the input of the
second shift register. Having passed through all
three shift registers the data is output on the
PSRout bus and can be used for cascading. Alter-
natively, as shown in Figure 2 the shift registers can
be bypassed and the input data transferred to the
PSRout bus after two delay stages. This mode can
be controlled via the on-chip control registers and
significantly simplifies software configuration of a
cascade arrangement.
4. MAC ARRAY
As shown in Figure 2, the processing core of the
device consists of a configurable array of multiply-
accumulators (macs). The mac array consists of
three 7-stage transversal filters which can be con-
figured either as a 21-stage linear pipeline or as a
3 × 7 two-dimensional window. The input data is
8 bits wide and is fed to the mac array via three
programmable shift registers.
The output of each shift register is supplied as input
to one of the three 7-stage transversal filters. For
each of the three transversal filters the associated
input data is fed simultaneously to all 7 mac stages.
At each stage the input sample is multiplied by a
coefficient stored in memory, and added to the
output of the previous stage delayed by one clock
cycle. The output of each 7-stage mac is fed, via a
delay stage, to the first stage in the next transversal
filter.
The coefficient word width in the mac array is 8 bits
wide. Two banks of coefficients are provided. At any
instant one set of coefficients is in use within the
mac array. The set in use is defined by the state of
the ‘Current Bank’ bit, ACR[0]. The other set can be
altered via the microprocessor interface. Once a
new set of coefficients has been loaded, the activi-
ties of the two coefficient banks can be inter-
changed without interrupting the flow of data. Alter-
natively, by setting the ‘continous bank swap’ bit
SCR[0], the two coefficient banks are swapped
automatically after each data input. In this case the
‘Current Bank’ bit only determines which bank is
used first. Both data input and coefficients can be
programmed independently to support twos com-
plement or positive unsigned formats allowing mul-
tiple devices to be used as a ‘slice’ in higher accu-
racy systems.
Within the mac array no truncation or rounding is
performed on the partial products. The mac array
output is fed to the backend post-processing unit
which is responsible for data transformation / nor-
malisation and cascading function.
5. BACKEND POST-PROCESSOR — hardware
description
The Backend Post-Processor consists of four ma-
jor blocks : The input block (shifter, cascade adder
and rectifier unit),a statistics monitor,the data con-
ditioning unit which itself consists of the data trans-
formation unit and the data normaliser, and the
output block (output adder and multiplexers).
A detailed diagram of the Backend Post-Processor
is given in Figure 4.
All operations performed in the backend are on
twos complement signed numbers unless other-
wise stated.
5/26
5 Page 
IMSA110
7. GLOSSARY
This section defines the meaning of terms used
elsewhere in this data sheet.
Arithmetic Shift
For a right shift, the most significant bit is always
copied into the most significant end of the result.
For example shifting right by 2:
01000101 → 00010001
11000101 → 11110001
For a left shift, the least significant bit will become
zero.
Note that left shifting can cause overflows and
these are not detected in the MAC output scalar or
the data normaliser.
Rounding
All rounding done within the IMS A110 is equivalent
to truncating after adding 1/2 LSB. (Rounding is
always applied in the positive direction). For exam-
ple for 8 bit twos complement numbers undergoing
a two bit right shift:
00000011 → 00000000 + 1 = 00000001 (rounded up)
00000010 → 00000000 + 1 = 00000001 (rounded up)
11111110 → 11111111 + 1 = 00000000 (rounded up)
00000001 → 00000000
(no rounding)
11111101 → 11111111
(no rounding)
Left shifts do not generate rounding.
Transversal Filter
A transversal filter is a calculation consisting of the
sum of products of successive points of input data.
For input data xi, xi+1, ..., and a set of coefficients,
c6,c5, ..., the result, Y is:
6
∑Y= ci × x6−i
i=0
Two’s Complement
Two’s complement numbers allow both positive
and negative numbers. For example in 8 bit num-
bers the most positive number is 127, the most
negative is -128:
two’s complement
10000000
10000001
11111111
00000000
00000001
01111111
decimal
-128
-127
-1
0
1
127
Rectification
Rectification is a method of removing negative
numbers. There are two methods: Full wave and
Half wave. In either case all positive numbers and
zero are unaffected. In Full wave rectification, any
negative numbers are negated (i.e. multiplied by 1)
so that they become positive. In Half wave rectifi-
cation, all negative numbers are replaced by zero.
Dynamic Range Compression
When Dynamic is used in this context, it is to
indicate a change of behaviour for each data point.
For example, a dynamic shift is one where the size
of the shift may change on each successive clock
cycle. Dynamic range compression is range com-
pression making use of an offset and shift, which
can change depending on each data point. This
allows the essential non-linear transformations re-
quired in image processing to be implemented on
the IMS A110.
Bit Fields
Bits, words and addresses in this data sheet are
little-endian; The lowest order byte of a multiple
byte word is referred to as byte 0, and is addressed
in the same way. Similarly, the least significant bit
of any bit field is that with the lowest bit number. For
example, ‘bits 26-22’ refers to a 5 bit field where bit
22 is treated as the least significant, and bit 26 as
the most significant.
Latency
Within the IMSA110 the latency is the number of
clock cycles from an input to its corresponding
output. For instance, with the programmable shift
registers bypassed by setting SCR[1] to 1, the
latency from PSRin to PSRout will be 2 as shown
in Figure 6.
11/26
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