IMP706ESA Datasheet PDF - IMP Inc
| Part Number | IMP706ESA | |
| Description | LOW-POWER P SUPERVISOR CIRCUITS | |
| Manufacturers | IMP Inc | |
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IMP705/6/7/8, 813L
POWER MANAGEMENT
Low-Power µP Supervisor Circuits
– Watchdog timer
– Brownout detection
– Power supply monitor
The IMP705/706/707/708 and IMP813L CMOS supervisor circuits
monitor power-supply and battery voltage level, and µP/µC operation.
Compared to pin-compatible devices offered by Maxim Integrated
Products, IMP devices feature 60 percent lower maximum supply current.
The family offers several functional options. Each device generates a
reset signal during power-up, power-down and during brownout
conditions. A reset is generated when the supply drops below
4.65V (IMP705/707/813L) or 4.40V (IMP706/708). For 3V power supply
applications, refer to the IMP705P/R/S/T data sheet. In addition, the
IMP705/706/813L feature a 1.6 second watchdog timer. The IMP707/708
have both active-HIGH and active-LOW reset outputs but no watchdog
function. The IMP813L has the same pin-out and functions as the IMP705
but has an active-HIGH reset output. A versatile power-fail circuit has a
1.25V threshold, useful in checking battery levels and non-5V supplies. All
devices have a manual reset (MR) input. The watchdog timer output will
trigger a reset if connected to MR.
All devices are available in 8-pin DIP, SO and MicroSO packages.
Block Diagrams
Key Features
N Improved replacements for the Maxim
MAX705/6/7/8, MAX813L
– 140µA maximum supply current
– 60% improvement
N Precision power supply monitor
– 4.65V threshold (IMP705/707/813L)
– 4.40V threshold (IMP706/8)
N Debounced manual reset input
N Voltage monitor
– 1.25V threshold
– Battery monitor/Auxiliary supply monitor
N Watchdog timer (IMP705/706/813L)
N 200ms reset pulse width
N Active HIGH reset output (IMP707/708/813L)
N MicroSO package
Applications
N Computers and embedded controllers
N Battery-operated systems
N Intelligent instruments
N Wireless communication systems
N PDAs and handheld equipment
WDI
Transition
Detector
VCC
0.25mA
Watchdog
Timer
Timebase
MR RESET
Generator
VCC
+
+
–
4.65V (IMP705/813L)
4.40V (IMP706)
PFI +
IMP705 1.25V
IMP706
IMP813L
–
WDO
RESET
(RESET)
(IMP813L)
PFO
MR
VCC
PFI
VCC
0.25mA
RESET
Generator
+
+–
4.65V (IMP707)
4.40V (IMP708)
IMP707
IMP708
1.25V
+
–
RESET
RESET
PFO
© 1999 IMP, Inc.
GND
705_01.eps
408-432-9100/www.impweb.com
GND
705_02.eps
1
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IMP705/6/7/8, 813L
Detail Descriptions
RESET/RESET Operation
The RESET/RESET signals are designed to start a µP/µC in a
known state or return the system to a known state.
The IMP707/708 have two RESET outputs, one active-HIGH
RESET and one active-LOW RESET output. The IMP813L has
only an active-HIGH output. RESET is simply the complement
of RESET.
RESET is guaranteed to be LOW with VCC above 1.2V. During a
power-up sequence, RESET remains low until the supply rises
above the threshold level, either 4.65V, 4.40V or 4.00V. RESET goes
high approximately 200ms after crossing the threshold.
During power-down, RESET goes LOW as VCC falls below the
threshold level and is guaranteed to be under 0.4V with VCC
above 1.2V.
Manual Reset (MR)
The active-LOW manual reset input is pulled high by a 250µA
pull-up current and can be driven low by CMOS/TTL logic or a
mechanical switch to ground. An external debounce circuit is
unnecessary since the 140ms minimum reset time will debounce
mechanical pushbutton switches.
By connecting the watchdog output (WDO) and MR, a watchdog
timeout forces RESET to be generated. The IMP813L should be
used when an active-HIGH RESET is required.
Watchdog Timer
The watchdog timer available on the IMP705/706/813L monitors
µP/µC activity. If activity is not detected within 1.6 seconds, the
internal timer puts the watchdog output, WDO, into a LOW
state. WDO will remain LOW until activity is detected at WDI.
In a brownout situation where VCC falls below the threshold
level, RESET pulses low. If a brownout occurs during an already-
initiated reset, the pulse will continue for a minimum of 140ms.
Auxiliary Comparator
All devices have an auxiliary comparator with 1.25V trip point
and uncommitted output (PFO) and noninverting input (PFI).
This comparator can be used as a supply voltage monitor with an
external resistor voltage divider. The attenuated voltage at PFI
should be set just below the 1.25 threshold. As the supply level
falls, PFI is reduced causing the PFO output to transit LOW.
Normally PFO interrupts the processor so the system can be shut
down in a controlled manner.
The watchdog function is disabled, meaning it is cleared and not
counting, if WDI is floated or connected to a three-stated circuit.
The watchdog timer is also disabled if RESET is asserted. When
RESET becomes inactive and the WDI input sees a high or low
transition as short as 50ns, the watchdog timer will begin a 1.6
second countdown. Additional transitions at WDI will reset the
watchdog timer and initiate a new countdown sequence.
WDO will also become LOW and remain so, whenever the
supply voltage, VCC , falls below the device threshold level. WDO
goes HIGH as soon as VCC transitions above the threshold. There
is no minimum pulse width for WDO as there is for the RESET
outputs. If WDI is floated, WDO essentially acts as a low-power
output indicator.
5V
VCC
0V
5V
RESET
0V
vRT
tRS
tRS
5V
WDI
0V
tWP
5V
WDO
0V
tWD
tWD
5V
MR
0V
5V
WDO
0V
MR extermally
set low
tMD
tMR
Figure 1. WDI Three-state operation
5V
RESET
0V
5V
(RESET)
IMP813L 0V
705_04.eps
RESET triggered by MR
tRS
Figure 2. Watchdog Timing
© 1999 IMP, Inc.
408-432-9100/www.impweb.com
tWD
705_05.eps
5
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