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PDF 12CE673 Data sheet ( Hoja de datos )
| Número de pieza | 12CE673 | |
| Descripción | 8-Pin/ 8-Bit CMOS Microcontroller with A/D Converter and EEPROM Data Memory | |
| Fabricantes | Microchip Technology | |
| Logotipo |  |
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M
PIC12CE67X
8-Pin, 8-Bit CMOS Microcontroller with A/D Converter
and EEPROM Data Memory
Devices Included in this Data Sheet:
• PIC12CE673
• PIC12CE674
High-Performance RISC CPU:
• Only 35 single word instructions to learn
• All instructions are single cycle (400 ns) except for
program branches which are two-cycle
• Operating speed: DC - 10 MHz clock input
DC - 400 ns instruction cycle
Device
Program
Memory
Data
RAM
Data
EEPROM
PIC12CE673 1024 x 14 128 x 8
16 x 8
PIC12CE674 2048 x 14 128 x 8
16 x 8
• 14-bit wide instructions
• 8-bit wide data path
• Interrupt capability
• Special function hardware registers
• 8-level deep hardware stack
• Direct, indirect and relative addressing modes for
data and instructions
Peripheral Features:
• Four-channel, 8-bit A/D converter
• 8-bit real time clock/counter (TMR0) with 8-bit
programmable prescaler
• Interrupt on pin change (GP0, GP1, GP3)
• 1,000,000 erase/write cycle EEPROM data
memory
• EEPROM data retention > 40 years
Pin Diagram:
PDIP, Windowed CERDIP
VDD
GP5/OSC1/CLKIN
GP4/OSC2/AN3/CLKOUT
GP3/MCLR/VPP
18
27
36
45
VSS
GP0/AN0
GP1/AN1/VREF
GP2/T0CKI/AN2/INT
Special Microcontroller Features:
• In-Circuit Serial Programming (ICSP™)
• Internal 4 MHz oscillator with programmable
calibration
• Selectable clockout
• Power-on Reset (POR)
• Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Programmable code protection
• Power saving SLEEP mode
• Internal pull-ups on I/O pins (GP0, GP1, GP3)
• Internal pull-up on MCLR pin
• Selectable oscillator options:
- INTRC: Precision internal 4 MHz oscillator
- EXTRC: External low-cost RC oscillator
- XT: Standard crystal/resonator
- HS: High speed crystal/resonator
- LP: Power saving, low frequency crystal
CMOS Technology:
• Low-power, high-speed CMOS EPROM/
EEPROM technology
• Fully static design
• Wide operating voltage range 2.5V to 5.5V
• Commercial, Industrial, and Extended
temperature ranges
• Low power consumption
< 2 mA @ 5V, 4 MHz
15 µA typical @ 3V, 32 kHz
< 1 µA typical standby current
© 1998 Microchip Technology Inc.
Preliminary
DS40181B-page 1
1 page  
2.0 PIC12CE67X DEVICE
VARIETIES
A variety of frequency ranges and packaging options
are available. Depending on application and production
requirements, the proper device option can be selected
using the information in the PIC12CE67X Product Iden-
tification System section at the end of this data sheet.
When placing orders, please use that page of the data
sheet to specify the correct part number.
For example, the PIC12CE67X device “type” is indi-
cated in the device number:
1. CE, as in PIC12CE674. These devices have
OTP program memory, EEPROM data memory
and operate over the standard voltage range.
2.1 UV Erasable Devices
The UV erasable version, offered in windowed pack-
age, is optimal for prototype development and pilot pro-
grams.
The UV erasable version can be erased and repro-
grammed to any of the configuration modes.
Microchip's PICSTART® Plus and PRO MATE® pro-
grammers both support the PIC12CE67X. Third party
programmers also are available; refer to the Microchip
Third Party Guide for a list of sources.
Note:
Please note that erasing the device will
also erase the pre-programmed internal
calibration value for the internal oscillator.
The calibration value must be saved prior
to erasing the part.
2.2 One-Time-Programmable (OTP)
Devices
The availability of OTP devices is especially useful for
customers who need the flexibility for frequent code
updates and small volume applications.
The OTP devices, packaged in plastic packages, per-
mit the user to program them once. In addition to the
program memory, the configuration bits must also be
programmed.
PIC12CE67X
2.3 Quick-Turn-Programming (QTP)
Devices
Microchip offers a QTP Programming Service for fac-
tory production orders. This service is made available
for users who choose not to program a medium to high
quantity of units and whose code patterns have stabi-
lized. The devices are identical to the OTP devices but
with all EPROM locations and configuration options
already programmed by the factory. Certain code and
prototype verification procedures apply before produc-
tion shipments are available. Please contact your local
Microchip Technology sales office for more details.
2.4 Serialized Quick-Turn Programming
(SQTPSM) Devices
Microchip offers a unique programming service where
a few user-defined locations in each device are pro-
grammed with different serial numbers. The serial num-
bers may be random, pseudo-random, or sequential.
Serial programming allows each device to have a
unique number which can serve as an entry-code,
password, or ID number.
© 1998 Microchip Technology Inc.
Preliminary
DS40181B-page 5
5 Page 
4.0 MEMORY ORGANIZATION
4.1 Program Memory Organization
The PIC12CE67X has a 13-bit program counter capa-
ble of addressing an 8K x 14 program memory space.
For the PIC12CE673 the first 1K x 14 (0000h-03FFh) is
implemented.
For the PIC12CE674, the first 2K x 14 (0000h-07FFh)
is implemented. Accessing a location above the physi-
cally implemented address will cause a wraparound.
The reset vector is at 0000h and the interrupt vector is
at 0004h.
FIGURE 4-1: PIC12CE67X PROGRAM
MEMORY MAP AND STACK
PC<12:0>
CALL, RETURN
RETFIE, RETLW
13
Stack Level 1
Stack Level 8
Reset Vector
0000h
PIC12CE67X
4.2 Data Memory Organization
The data memory is partitioned into two Banks which
contain the General Purpose Registers and the Special
Function Registers. Bit RP0 is the bank select bit.
RP0 (STATUS<5>) = 1 → Bank 1
RP0 (STATUS<5>) = 0 → Bank 0
Each Bank extends up to 7Fh (128 bytes). The lower
locations of each Bank are reserved for the Special
Function Registers. Above the Special Function Regis-
ters are General Purpose Registers implemented as
static RAM. Both Bank 0 and Bank 1 contain special
function registers. Some "high use" special function
registers from Bank 0 are mirrored in Bank 1 for code
reduction and quicker access.
Also note that F0h through FFh on the PIC12CE67X is
mapped into Bank 0 registers 70h-7Fh as common
RAM.
4.2.1 GENERAL PURPOSE REGISTER FILE
The register file can be accessed either directly, or indi-
rectly through the File Select Register FSR
(Section 4.5).
Peripheral Interrupt Vector 0004h
0005h
On-chip Program
Memory
(PIC12CE674 only)
03FFh
0400h
07FFh
0800h
1FFFh
© 1998 Microchip Technology Inc.
Preliminary
DS40181B-page 11
11 Page | ||
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