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PDF K9K1G08U0B Data sheet ( Hoja de datos )
| Número de pieza | K9K1G08U0B | |
| Descripción | 128M x 8 Bit NAND Flash Memory | |
| Fabricantes | Samsung semiconductor | |
| Logotipo |  |
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K9K1G08R0B
K9K1G08B0B
K9K1G08U0B
Document Title
128M x 8 Bit NAND Flash Memory
Advance
FLASH MEMORY
Revision History
Revision No. History
0.0 Initial issue.
0.1 1. Note 1 ( Program/Erase Characteristics) is added( page 13 )
2. NAND Flash Technical Notes is changed.
-Invalid block -> initial invalid block ( page 15 )
-Error in write or read operation ( page 16 )
-Program Flow Chart ( page 16 )
3. Vcc range is changed
-1.7V~1.95V ->1.65V~1.95V
4. 2.7V device is added
5. Multi plane operation and Copy-Back Program are not supported with 1.8V
device.
Draft Date Remark
Mar. 17th 2003 Advance
Oct. 11th 2004 Advance
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near your office.
1
1 page  
K9K1G08R0B
K9K1G08B0B
K9K1G08U0B
Advance
FLASH MEMORY
PIN DESCRIPTION
Pin Name
I/O0 ~ I/O7
(K9K1G08X0B)
Pin Function
DATA INPUTS/OUTPUTS
The I/O pins are used to input command, address and data, and to output data during read operations. The I/
O pins float to high-z when the chip is deselected or when the outputs are disabled.
COMMAND LATCH ENABLE
CLE The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
ADDRESS LATCH ENABLE
ALE The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE with ALE high.
CHIP ENABLE
CE
The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and
the device does not return to standby mode in program or erase operation. Regarding CE control during
read operation, refer to ’Page read’ section of Device operation .
READ ENABLE
RE The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE which also increments the internal column address counter by one.
WRITE ENABLE
WE The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of
the WE pulse.
WRITE PROTECT
WP The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage
generator is reset when the WP pin is active low.
READY/BUSY OUTPUT
R/B
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or
random read operation is in process and returns to high state upon completion. It is an open drain output and
does not float to high-z condition when the chip is deselected or when outputs are disabled.
VccQ
OUTPUT BUFFER POWER
VccQ is the power supply for Output Buffer.
VccQ is internally connected to Vcc, thus should be biased to Vcc.
Vcc
POWER
VCC is the power supply for device.
Vss GROUND
N.C
NO CONNECTION
Lead is not internally connected.
DNU
DO NOT USE
Leave it disconnected.
NOTE : Connect all VCC and VSS pins of each device to common power supply outputs.
Do not leave VCC or VSS disconnected.
5
5 Page 
K9K1G08R0B
K9K1G08B0B
K9K1G08U0B
Advance
FLASH MEMORY
AC TEST CONDITION
(K9K1G08X0B-XCB0 :TA=0 to 70°C, K9K1G08X0B-XIB0 :TA=-40 to 85°C
K9K1G08R0B : Vcc=1.65V~1.95V , K9K1G08B0B : Vcc=2.5V~2.9V, K9K1G08U0B : Vcc=2.7V~3.6V unless otherwise noted)
Parameter
K9K1G08R0B
K9K1G08B0B
K9K1G08U0B
Input Pulse Levels
0V to VccQ
0V to VccQ
0.4V to 2.4V
Input Rise and Fall Times
5ns 5ns
5ns
Input and Output Timing Levels
VccQ/2
VccQ/2
1.5V
K9K1G08R0B:Output Load (VccQ:1.8V +/-10%)
K9K1G08B0C:Output Load (VccQ:2.7V +/-10%) 1 TTL GATE and CL=30pF 1 TTL GATE and CL=30pF 1 TTL GATE and CL=50pF
K9K1G08U0B:Output Load (VccQ:3.0V +/-10%)
K9K1G08U0B:Output Load (VccQ:3.3V +/-10%)
-
- 1 TTL GATE and CL=100pF
Capacitance(TA=25°C, VCC=1.8V/2.7V/3.3V, f=1.0MHz)
Item
Input/Output Capacitance
Input Capacitance
Symbol
CI/O
CIN
Test Condition
VIL=0V
VIN=0V
NOTE : Capacitance is periodically sampled and not 100% tested.
Min
-
-
Max
20
20
MODE SELECTION
CLE
H
L
H
L
L
L
X
ALE
L
H
L
H
L
L
X
CE WE RE
LH
LH
LH
LH
LH
LH
X XH
WP Mode
X
Read Mode
Command Input
X Address Input(4clock)
H
Write Mode
Command Input
H Address Input(4clock)
H Data Input
X Data Output
X During Read(Busy) on the devices
X X X X X H During Program(Busy)
X X X X X H During Erase(Busy)
X X(1) X X X L Write Protect
X X H X X 0V/VCC(2) Stand-by
NOTE : 1. X can be VIL or VIH.
2. WP should be biased to CMOS high or CMOS low for standby.
Unit
pF
pF
Program / Erase Characteristics
Parameter
Symbol
Min
Typ
Max Unit
Program Time
tPROG(1)
-
200 500
µs
Dummy Busy Time for Multi Plane Program
tDBSY
1 10 µs
Number of Partial Program Cycles
in the Same Page
Main Array
Spare Array
Nop
-
-
-
-
1 cycle
2 cycles
Block Erase Time
tBERS
-
2
3 ms
NOTE : 1.Typical program time is defined as the time within which more than 50% of the whole pages are programmed at Vcc of 3.3V and 25’C
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet K9K1G08U0B.PDF ] | |
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