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Samsung semiconductor - 4M x 16bit CMOS Dynamic RAM with Extended Data Out

Numéro de référence KM416V4104B
Description 4M x 16bit CMOS Dynamic RAM with Extended Data Out
Fabricant Samsung semiconductor 
Logo Samsung semiconductor 





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KM416V4104B fiche technique
KM416V4004B, KM416V4104B
CMOS DRAM
4M x 16bit CMOS Dynamic RAM with Extended Data Out
DESCRIPTION
This is a family of 4,194,304 x 16 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random
access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -5 or -6), power consumption(Normal
or Low power) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh
capabilities. Furthermore, Self-refresh operation is available in L-version. This 4Mx16 EDO Mode DRAM family is fabricated using Sam-
sungs advanced CMOS process to realize high band-width, low power consumption and high reliability.
FEATURES
• Part Identification
- KM416V4004B/B-L(3.3V, 8K Ref.)
- KM416V4104B/B-L(3.3V, 4K Ref.)
Active Power Dissipation
Speed
-45
-5
-6
8K
360
324
288
Unit : mW
4K
468
432
396
Refresh Cycles
Part
NO.
KM416V4004B*
KM416V4104B
Refresh
cycle
8K
4K
Refresh time
Normal L-ver
64ms 128ms
* Access mode & RAS only refresh mode
: 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.)
CAS-before-RAS & Hidden refresh mode
: 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)
Performance Range
Speed tRAC
tCAC
-45 50ns 12ns
-5 50ns 13ns
-6 60ns 15ns
tRC
74ns
84ns
104ns
tHPC
17ns
20ns
25ns
• Extended Data Out Mode operation
• 2 CAS Byte/Word Read/Write operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Fast parallel test mode capability
• Self-refresh capability (L-ver only)
• LVTTL(3.3V) compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in Plastic TSOP(II) packages
• +3.3V±0.3V power supply
FUNCTIONAL BLOCK DIAGRAM
RAS
UCAS
LCAS
W
Control
Clocks
VBB Generator
Refresh Timer
Refresh Control
Refresh Counter
A0~A12
(A0~A11)*1
A0~A8
(A0~A9)*1
Row Address Buffer
Col. Address Buffer
Note) *1 : 4K Refresh
Row Decoder
Memory Array
4,194,304 x 16
Cells
Column Decoder
Vcc
Vss
Lower
Data in
Buffer
Lower
Data out
Buffer
Upper
Data in
Buffer
Upper
Data out
Buffer
DQ0
to
DQ7
OE
DQ8
to
DQ15
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.

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