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KM416V1000C fiches techniques PDF

Samsung semiconductor - 1M x 16Bit CMOS Dynamic RAM with Fast Page Mode

Numéro de référence KM416V1000C
Description 1M x 16Bit CMOS Dynamic RAM with Fast Page Mode
Fabricant Samsung semiconductor 
Logo Samsung semiconductor 





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KM416V1000C fiche technique
KM416C1000C, KM416C1200C
KM416V1000C, KM416V1200C
CMOS DRAM
1M x 16Bit CMOS Dynamic RAM with Fast Page Mode
DESCRIPTION
This is a family of 1,048,576 x 16 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory
cells within the same row. Power supply voltage (+5.0V or +3.3V), refresh cycle (1K Ref. or 4K Ref.), access time (-5 or -6), power con-
sumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-
before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This
1Mx16 Fast Page Mode DRAM family is fabricated using Samsungs advanced CMOS process to realize high band-width, low power
consumption and high reliability. It may be used as graphic memory unit for microcomputer, personal computer and portable machines.
FEATURES
• Part Identification
- KM416C1000C/C-L (5V, 4K Ref.)
- KM416C1200C/C-L (5V, 1K Ref.)
- KM416V1000C/C-L (3.3V, 4K Ref.)
- KM416V1200C/C-L (3.3V, 1K Ref.)
Active Power Dissipation
Speed
-5
-6
3.3V
4K 1K
324 504
288 468
Unit : mW
5V
4K 1K
495 770
440 715
Refresh Cycles
Part VCC Refresh
NO. cycle
C1000C
V1000C
C1200C
V1200C
5V
3.3V
5V
3.3V
4K
1K
Refresh period
Normal L-ver
64ms
16ms
128ms
Perfomance Range
Speed tRAC tCAC
-5 50ns 15ns
-6 60ns 15ns
tRC
90ns
110ns
tPC
35ns
40ns
Remark
5V/3.3V
5V/3.3V
• Fast Page Mode operation
• 2 CAS Byte/Word Read/Write operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• TTL(5V)/LVTTL(3.3V) compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in 42-pin SOJ 400mil and 50(44)-pin TSOP(II)
400mil packages
• Single +5V±10% power supply (5V product)
• Single +3.3V±0.3V power supply (3.3V product)
FUNCTIONAL BLOCK DIAGRAM
RAS
UCAS
LCAS
W
Control
Clocks
VBB Generator
A0-A11
(A0 - A9) *1
A0 - A7
(A0 - A9) *1
Refresh Timer
Refresh Control
Refresh Counter
Row Address Buffer
Col. Address Buffer
Row Decoder
Memory Array
1,048,576 x16
Cells
Column Decoder
Note) *1 : 1K Refresh
Vcc
Vss
Lower
Data in
Buffer
Lower
Data out
Buffer
Upper
Data in
Buffer
Upper
Data out
Buffer
DQ0
to
DQ7
OE
DQ8
to
DQ15
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.

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