PDF KM4132G271A Data sheet ( Hoja de datos )

Número de pieza	KM4132G271A
Descripción	128K x 32Bit x 2 Banks Synchronous Graphic RAM
Fabricantes	Samsung semiconductor
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No Preview Available ! KM4132G271A CMOS SGRAM 128K x 32Bit x 2 Banks Synchronous Graphic RAM FEATURES ¡Ü JEDEC standard 3.3V power supply ¡Ü LVTTL compatible with multiplexed address ¡Ü Dual bank / Pulse RAS ¡Ü MRS cycle with address key programs -. CAS Latency (2, 3) -. Burst Length (1, 2, 4, 8 & full page) -. Burst Type (Sequential & Interleave) ¡Ü All inputs are sampled at the positive going edge of the system clock ¡Ü Burst Read Single-bit Write operation ¡Ü DQM 0-3 for byte masking ¡Ü Auto & self refresh ¡Ü 16ms refresh period (1K cycle) ¡Ü 100 Pin QFP Graphics Features ¡Ü SMRS cycle. -. Load mask register -. Load color register ¡Ü Write Per Bit(Old Mask) ¡Ü Block Write(8 Columns) GENERAL DESCRIPTION The KM4132G271A is 8,388,608 bits synchronous high data rate Dynamic RAM organized as 2 x 131,072 words by 32 bits, fabricated with SAMSUNG's high performance CMOS technol- ogy. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length, and programmable latencies allows the same device to be useful for a variety of high bandwidth, high perfor- mance memory system applications. Write per bit and 8 columns block write improves performance in graphics systems. ORDERING INFORMATION Part NO. KM4132G271A-8 KM4132G271A-10 KM4132G271A-12 Cycle time 8ns 10ns 12ns Clock f 125MHz 100MHz 83MHz Access time@CL=3 7.0ns 7.0ns 9.0ns FUNCTIONAL BLOCK DIAGRAM CLK CKE CS DQMi BLOCK WRITE CONTROL LOGIC COLUMN MASK WRITE CONTROL LOGIC MUX MASK REGISTER COLOR REGISTER DQMi RAS CAS WE 128Kx32 CELL ARRAY 128Kx32 CELL ARRAY DSF DQMi SERIAL COUNTER COLUMN ADDRESS BUFFER ROW DECORDER BANK SELECTION ROW ADDRESS BUFFER REFRESH COUNTER ADDRESS REGISTER CLOCK ADDRESS(A0~A9) DQi (i=0~31) Rev.0 (August 1997) 1 page KM4132G271A CMOS SGRAM DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, TA = 0 to 70¡É VIH(min)/VIL(max)=2.0V/0.8V) Parameter Symbol Test Condition CAS Latency Operating Current (One Bank Active) ICC1 Precharge Standby Cur- rent in power-down mode ICC2P ICC2PS Precharge Standby Current in non power-down mode ICC2N ICC2NS Active Standby Current in power-down mode Active Standby Current in non power-down mode (One Bank Active) ICC3P ICC3PS ICC3N ICC3NS Operating Current (Burst Mode) ICC4 Refresh Current Self Refresh Current Operating Current (One Bank Block Write) ICC5 ICC6 ICC7 Burst Length =1 tRC¡ÃtRC(min), tCC¡ÃtCC(min) IOL = 0 mA CKE¡ÂVIL(max), tCC = 15ns 3 2 CKE¡ÂVIL(max), CLK¡ÂVIL(max), tCC = ¡Ä CKE¡ÃVIH(min), CS¡ÃVIH(min), tCC = 15ns Input signals are changed one time during 30ns CKE¡ÃVIH(min), CLK¡ÂVIL(max), tCC = ¡Ä Input signals are stable CKE¡ÂVIL(max), tCC = 15ns CKE¡ÂVIL(max), CLK¡ÂVIL(max), tCC = ¡Ä CKE¡ÃVIH(min), CS¡ÃVIH(min), tCC = 15ns Input signals are changed one time during 30ns CKE¡ÃVIH(min), CLK¡ÂVIL(max), tCC = ¡Ä Input signals are stable IOL = 0 mA, Page Burst All bank Activated, tCCD = tCCD(min) tRC¡ÃtRC(min) CKE¡Â0.2V 3 2 3 2 tCC¡ÃtCC(min), IOL=0mA, tBWC(min) Speed -8 -10 -12 180 160 140 160 140 120 222 222 45 45 45 20 20 20 444 3.5 3.5 3.5 55 55 55 35 35 35 200 180 160 180 160 140 140 120 100 130 110 90 111 170 150 130 Unit Note mA 1 mA mA mA mA mA 1, 2 mA 3 mA mA 4 Note : 1. Measured with outputs open. 2. Assumes minimum column address update cycle tCCD(min). 3. Refresh period is 16ms. 4. Assumes minimum column address update cycle tBWC(min). Rev.0 (August 1997) 5 Page KM4132G271A CMOS SGRAM MODE REGISTER FIELD TABLE TO PROGRAM MODES Register Programmed with MRS Address A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Function W.B.L (Note 1) TM CAS Latency BT Burst Length Test Mode CAS Latency A8 A7 Type A6 A5 A4 Latency 0 0 Mode Register Set 0 0 0 Reserved 01 10 11 Vendor Use Only 001 010 011 - 2 3 Write Burst Length 1 0 0 Reserved A9 Length 1 0 1 Reserved 0 Burst 1 1 0 Reserved 1 Single Bit 1 1 1 Reserved Burst Type A3 Type 0 Sequential 1 Interleave Burst Length A2 A1 A0 BT=0 000 1 001 2 010 4 011 8 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 256(Full) BT=1 Reserved Reserved 4 8 Reserved Reserved Reserved Reserved (Note 2) Special Mode Register Programmed with SMRS Address A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Function X LC LM X Load Color A6 Function 0 Disable 1 Enable Load Mask A5 Function 0 Disable 1 Enable (Note 3) POWER UP SEQUENCE 1. Apply power and start clock, Attempt to maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs. 2. Maintain stable power, stable clock and NOP input condition for a minimum of 200§Á. 3. Issue precharge commands for all banks of the devices. 4. Issue 2 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. cf.) Sequence of 4 & 5 may be changed. The device is now ready for normal operation. Note : 1. If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled. 2. The full column burst(256bit) is available only at Sequential mode of burst type. 3. If LC and LM both high(1), data of mask and color register will be unknown. Rev.0 (August 1997) 11 Page

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