IDT74FCT623ATP Datasheet PDF - Integrated Device Technology
| Part Number | IDT74FCT623ATP | |
| Description | FAST CMOS OCTAL BUS TRANSCEIVERS (3-STATE) | |
| Manufacturers | Integrated Device Technology | |
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There is a preview and IDT74FCT623ATP download ( pdf file ) link at the bottom of this page. Total 6 Pages | ||
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IDT54/74FCT623T/AT/CT
FAST CMOS OCTAL BUS TRANSCEIVERS (3-STATE)
FAST CMOS OCTAL
BUS TRANSCEIVERS
Integrated Device Technology, Inc.
(3-STATE)
IDT54/74FCT623T/AT/CT
FEATURES:
• Std., A and C speed grades
• Low input and output leakage ≤1µA (max.)
• CMOS power levels
• True TTL input and output compatibility
– VOH = 3.3V (typ.)
– VOL = 0.3V (typ.)
• High drive outputs (-15mA IOH, 64mA IOL)
• Power off disable outputs permit “live insertion”
• Meets or exceeds JEDEC standard 18 specifications
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
and DESC listed (dual marked)
• Available in DIP, SOIC, CERPACK and LCC packages
DESCRIPTION
The FCT623T/AT/CT is a non-inverting octal transceiver
with 3-state bus-driving outputs in both the send and receive
directions. The B bus outputs are capable of sinking 64mA and
sourcing up to 15mA, providing very good capacitive drive
characteristics.
These octal bus transceivers are designed for asynchro-
nous two-way communication between data buses. The control
function implementation allows for maximum flexibility in
timing.
One important feature of the FCT623T/AT/CT is the Power
GDown Disable capability. When the GAB and BA inputs are
conditioned to put the device in high-Z state, the I/O ports will
maintain high impedance during power supply ramps and
when VCC = 0V. This is a desirable feature in back-plane
applications where it may be necessary to perform “live”
insertion and removal of cards for on-line maintenance. It is
also a benefit in systems with multiple redundancy where one
or more redundant cards may be powered-off.
FUNCTIONAL BLOCK DIAGRAM
GBA
GAB
A1
B1
A2 - A8
7 other transceivers
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
6.19
6.19
B2 - B8
2563 drw 01
NOVEMBER 1995
DSC-2563/5
1
1
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IDT54/74FCT623T/AT/CT
FAST CMOS OCTAL BUS TRANSCEIVERS (3-STATE)
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
V CC
VIN
Pulse
Generator
D.U.T.
RT
V OUT
50pF
CL
500Ω
500Ω
7.0V
SWITCH POSITION
Test
Switch
Open Drain
Disable Low
Closed
Enable Low
All Other Tests
Open
DEFINITIONS:
2563 lnk 09
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
2563 drw 05
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
tSU
tSU
tH
tREM
tH
PROPAGATION DELAY
SAME PHASE
INPUT TRANSITION
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
tPLH
tPLH
tPHL
tPHL
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
LOW-HIGH-LOW
PULSE
HIGH-LOW-HIGH
PULSE
tW
1.5V
1.5V
3V
1.5V
0V
2563 drw 07
2563 drw 06
ENABLE AND DISABLE TIMES
3V
1.5V
0V
VOH
1.5V
VOL
3V
1.5V
0V
2563 drw 08
ENABLE
DISABLE
CONTROL
INPUT
OUTPUT
NORMALLY
LOW
tPZL
SWITCH
CLOSED
tPZH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
3V
1.5V
0V
tPLZ
3.5V
3.5V
1.5V
tPHZ
0.3V VOL
1.5V
0.3V VOH
0V 0V
NOTES:
2563 drw 09
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
6.19 5
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for IDT74FCT623ATP electronic component. |
| Information | Total 6 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ IDT74FCT623ATP.PDF Datasheet ] | |
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