IDT74FCT388915T150PYB Datasheet PDF - Integrated Device Technology
| Part Number | IDT74FCT388915T150PYB | |
| Description | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) | |
| Manufacturers | Integrated Device Technology | |
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IDT54/74FCT388915T 70/100/133/150
3.3V LOW SKEW PLL-BASED CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Integrated Device Technology, Inc.
3.3V LOW SKEW PLL-BASED
CMOS CLOCK DRIVER
(WITH 3-STATE)
IDT54/74FCT388915T
70/100/133/150
PRELIMINARY
FEATURES:
• 0.5 MICRON CMOS Technology
• Input frequency range: 10MHz – f2Q Max. spec
(FREQ_SEL = HIGH)
• Max. output frequency: 150MHz
• Pin and function compatible with FCT88915T, MC88915T
• 5 non-inverting outputs, one inverting output, one 2x
output, one ÷2 output; all outputs are TTL-compatible
• 3-State outputs
• Output skew < 350ps (max.)
• Duty cycle distortion < 500ps (max.)
• Part-to-part skew: 1ns (from tPD max. spec)
• 32/–16mA drive at CMOS output voltage levels
• VCC = 3.3V ± 0.3V
• Inputs can be driven by 3.3V or 5V components
• Available in 28 pin PLCC, LCC and SSOP packages
DESCRIPTION:
The IDT54/74FCT388915T uses phase-lock loop technol-
ogy to lock the frequency and phase of outputs to the input
reference clock. It provides low skew clock distribution for
high performance PCs and workstations. One of the outputs
is fed back to the PLL at the FEEDBACK input resulting in
essentially zero delay across the device. The PLL consists of
the phase/frequency detector, charge pump, loop filter and
VCO. The VCO is designed for a 2Q operating frequency
range of 40MHz to f2Q Max.
The IDT54/74FCT388915T provides 8 outputs with 350ps
skew. The Q5 output is inverted from the Q outputs. The 2Q
runs at twice the Q frequency and Q/2 runs at half the Q
frequency.
The FREQ_SEL control provides an additional ÷ 2 option in
the output path. PLL _EN allows bypassing of the PLL, which
is useful in static test modes. When PLL_EN is low, SYNC
input may be used as a test clock. In this test mode, the input
frequency is not limited to the specified range and the polarity
of outputs is complementary to that in normal operation
(PLL_EN = 1). The LOCK output attains logic HIGH when the
PLL is in steady-state phase and frequency lock. When OE/
RST is low, all the outputs are put in high impedance state and
registers at Q, Q and Q/2 outputs are reset.
The IDT54/74FCT388915T requires one external loop filter
component as recommended in Figure 3.
FUNCTIONAL BLOCK DIAGRAM
FEEDBACK
LOCK
SYNC (0)
SYNC (1)
REF_SEL
PLL_EN
0M
u
1x
FREQ_SEL
OE/RST
Phase/Freq.
Detector
Charge Pump
01
Mux
Divide
-By-2
(÷1)
(÷2)
1M
u
0x
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1995 Integrated Device Technology, Inc.
9.8
9.8
Voltage
Controlled
Oscilator
DQ
CP R Q
DQ
CP R
DQ
CP R
DQ
CP R
DQ
CP R
DQ
CP R
DQ
CP R
LF
2Q
Q0
Q1
Q2
Q3
Q4
Q5
Q/2
3052 drw 01
AUGUST 1995
DSC-4243/1
11
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IDT54/74FCT388915T 70/100/133/150
3.3V LOW SKEW PLL-BASED CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol
Parameter
Condition(1)
Min.*
Max.*
Unit
tRISE/FALL
All Outputs
tPULSE WIDTH (3)
Q, Q, Q/2 outputs(3)
tPULSE WIDTH
2Q Output(3)
Rise/Fall Time
(between 0.8V and 2.0V)
Output Pulse Width
Q0-Q4, Q5, Q/2, @ 1.5V
Output Pulse Width
2Q @ 1.5V
Load = 50Ω to
VCC/2, CL = 20pF
Load = 50Ω to
VCC/2, CL = 20pF
0.2(2)
0.5tCYCLE – 0.5(5)
0.5tCYCLE – 0.7(5)
1.5
0.5tCYCLE + 0.5(5)
0.5tCYCLE + 0.7(5)
ns
ns
ns
tPD SYNC input to FEEDBACK delay
SYNC-FEEDBACK(3) (measured at SYNC0 or 1 and FEEDBACK
input pins)
Load = 50Ω to
VCC/2, CL = 20pF
0.1µF from LF to
Analog GND(5)
–0.5
+0.5 ns
tSKEWr
(rising)(3,4)
Output to Output Skew
between outputs 2Q, Q0-Q4,
Load = 50Ω to
VCC/2, CL = 20pF
—
250 ps
Q/2 (rising edges only)
tSKEWf
(falling)(3,4)
tSKEWall (3,4)
tLOCK(6)
Output to Output Skew
between outputs Q0-Q4 (falling edges only)
Output to Output Skew
2Q, Q/2, Q0-Q4 rising, Q5 falling
Time required to acquire
— 250 ps
— 350 ps
1(2) 10 ms
Phase-Lock from time
SYNC input signal is received
tPZH Output Enable Time
tPZL OE/RST (LOW-to-HIGH) to Q, 2Q, Q/2, Q
tPHZ Output Disable Time
tPLZ OE/RST (HIGH-to-LOW) to Q, 2Q, Q/2, Q
3(2) 14 ns
3(2) 14 ns
GENERAL AC SPECIFICATION NOTES:
3052 tbl 08
* PRELIMINARY.
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested.
3. These specifications are guaranteed but not production tested.
4. Under equally loaded conditions, as specified under test conditions and at a fixed temperature and voltage.
5. tCYCLE = 1/frequency at which each output (Q, Q, Q/2 or 2Q) is expected to run.
6. With VCC fully powered-on and an output properly connected to the FEEDBACK pin. tLOCK Max. is with C1 = 0.1µF, tLOCK Min. is with C1 = 0.01µF. (Where
C1 is loop filter capacitor shown in Figure 2).
9.8 5
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| Part Number | Description | MFRS |
| IDT74FCT388915T150PY | The function is 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE). Integrated Device Technology | |
| IDT74FCT388915T150PYB | The function is 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE). Integrated Device Technology | |
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