IDT71256SA20Y Datasheet PDF - Integrated Device Technology
| Part Number | IDT71256SA20Y | |
| Description | CMOS STATIC RAM 256K (32K x 8-BIT) | |
| Manufacturers | Integrated Device Technology | |
| Logo |  |
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Integrated Device Technology, Inc.
CMOS STATIC RAM
256K (32K x 8-BIT)
IDT71256SA
FEATURES:
• 32K x 8 advanced high-speed CMOS static RAM
• Commercial (0° to 70°C) and Industrial (-40° to 85°C)
temperature options
• Equal access and cycle times
— Commercial: 12/15/20/25ns
— Industrial: 15/20ns
• One Chip Select plus one Output Enable pin
• Bidirectional data inputs and outputs directly
TTL-compatible
• Low power consumption via chip deselect
• Commercial product available in 28-pin 300- and 600-mil
Plastic DIP, 300 mil Plastic SOJ and TSOP packages
• Industrial product available in 28-pin 300 mil Plastic SOJ
and TSOP packages
DESCRIPTION:
The ID71256SA is a 262,144-bit high-speed Static RAM
organized as 32K x 8. It is fabricated using IDT’s high-
perfomance, high-reliability CMOS technology. This state-of-
the-art technology, combined with innovative circuit design
techniques, provides a cost-effective solution for high-speed
memory needs.
The IDT71256SA has an output enable pin which operates
as fast as 6ns, with address access times as fast as 12ns. All
bidirectional inputs and outputs of the IDT71256SA are TTL-
compatible and operation is from a single 5V supply. Fully
static asynchronous circuitry is used, requiring no clocks or
refresh for operation.
The IDT71256SA is packaged in 28-pin 300- and 600-mil
Plastic DIP, 28-pin 300 mil Plastic SOJ and TSOP.
FUNCTIONAL BLOCK DIAGRAM
A0
A1
A2
A3
A4
A5
A6 ADDRESS
A7
A8 DECODER
A9
A10
A11
A12
A13
A14
I/O 0 – I/O7 8
8
262,144-BIT
MEMORY
ARRAY
I/O CONTROL
CS CONTROL
WE LOGIC
OE
2948 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
©1997 Integrated Device Technology, Inc.
MAY 1997
DSC-2948/04
1
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IDT71256SA
CMOS STATIC RAM 256K (32K x 8-BIT)
INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)
tRC
ADDRESS
tAA
tOH
DATAOUT
PREVIOUS DATAOUT VALID
tOH
DATAOUT VALID
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter.
4. OE is LOW.
5. Transition is measured ±200mV from steady state.
2948 drw 06
TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING)(1,2,3,5)
ADDRESS
CS
WE
DATAOUT
DATAIN
tWC
tAW
tAS
tWP(3)
tWR
tWHZ (6)
tOW (6)
(4) HIGH IMPEDANCE
tDH
tDW
DATAIN VALID
tCHZ (6)
(4)
2948 drw 07
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING)(1,2,5)
tWC
ADDRESS
tAW
CS
tAS
tCW
tWR
WE
tDW
tDH
DATAIN
DATAIN VALID
2948 drw 08
NOTES:
1. WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap of a LOW CS and a LOW WE.
3. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn
off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the
minimum write pulse is as short as the specified tWP.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
6. Transition is measured ±200mV from steady state.
5
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| Information | Total 6 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ IDT71256SA20Y.PDF Datasheet ] | |
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