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PDF IDT71124 Data sheet ( Hoja de datos )
| Número de pieza | IDT71124 | |
| Descripción | CMOS Static RAM 1 Meg (128K x 8-Bit) Revolutionary Pinout | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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CMOS Static RAM
1 Meg (128K x 8-Bit)
Revolutionary Pinout
IDT71124
Features
◆ 128K x 8 advanced high-speed CMOS static RAM
◆ JEDEC revolutionary pinout (center power/GND) for
reduced noise.
◆ Equal access and cycle times
– Commercial: 12/15/20ns
– Industrial: 15/20ns
◆ One Chip Select plus one Output Enable pin
◆ Bidirectional inputs and outputs directly TTL-compatible
◆ Low power consumption via chip deselect
◆ Available in a 32-pin 400 mil Plastic SOJ.
Description
The IDT71124 is a 1,048,576-bit high-speed static RAM organized as
128K x 8. It is fabricated using high-performance, high-reliability CMOS
technology. This state-of-the-art technology, combined with innovative
circuitdesigntechniques,providesa cost-effectivesolutionforhigh-speed
memory needs. The JEDEC centerpower/GND pinout reduces noise
generation and improves system performance.
The IDT71124 has an output enable pin which operates as fast as 6ns,
with address access times as fast as 12ns available. All bidirectional inputs
and outputs of the IDT71124 are TTL-compatible and operation is from
a single 5V supply. Fully static asynchronous circuitry is used; no clocks
or refreshes are required for operation.
The IDT71124 is packaged in a 32-pin 400 mil Plastic SOJ.
Functional Block Diagram
A0
•
•
•
A16
ADDRESS
DECODER
•
•
•
1,048,576-BIT
MEMORY ARRAY
I/O0 - I/O7
•
8
8
WE
OE CONTROL
CS LOGIC
I/O CONTROL
8
,
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©2013 Integrated Device Technology, Inc.
1
APRIL 2013
DSC-3514/11
1 page  
IDT 71124 CMOS Static RAM
1 Meg (128K x 8-bit) Revolutionary Pinout
Timing Waveform of Read Cycle No. 1(1)
ADDRESS
OE
CS
DATAOUT
VCC SUPPLY ICC
CURRENT ISB
tRC
tAA
tOE
tOLZ (5)
tCLZ (5)
tACS (3)
HIGH IMPEDANCE
tPU
Commercial and Industrial Temperature Ranges
tOHZ (5)
tCHZ (5)
DATAOUT VALID
tPD
.
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Timing Waveform of Read Cycle No. 2(1,2,4)
ADDRESS
DATAOUT
tRC
tOH
PREVIOUS DATAOUT VALID
tAA
tOH
DATAOUT VALID
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter.
4. OE isLOW.
5. Transition is measured ±200mV from steady state.
.
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5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet IDT71124.PDF ] | |
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