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Integrated Device Technology - HIGH-SPEED 3.3V 128K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM

Numéro de référence IDT70V639S
Description HIGH-SPEED 3.3V 128K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM
Fabricant Integrated Device Technology 
Logo Integrated Device Technology 





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IDT70V639S fiche technique
HIGH-SPEED 3.3V 128K x 18
ASYNCHRONOUS DUAL-PORT
STATIC RAM
PRELIMINARY
IDT70V639S
Features
x True Dual-Port memory cells which allow simultaneous
access of the same memory location
x High-speed access
– Commercial: 10/12/15ns (max.)
– Industrial: 12/15ns (max.)
x Dual chip enables allow for depth expansion without
external logic
x IDT70V639 easily expands data bus width to 36 bits or
more using the Master/Slave select when cascading more
than one device
x M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
x Busy and Interrupt Flags
x On-chip port arbitration logic
x Full on-chip hardware support of semaphore signaling
between ports
Functional Block Diagram
UBL
LBL
R/WL
CE0 L
CE1L
x Fully asynchronous operation from either port
x Separate byte controls for multiplexed bus and bus
matching compatibility
x Supports JTAG features compliant to IEEE 1149.1
– Due to limited pin count, JTAG is not supported on the
128-pin TQFP package.
x LVTTL-compatible, single 3.3V (±150mV) power supply for
core
x LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)
power supply for I/Os and control signals on each port
x Available in a 128-pin Thin Quad Flatpack, 208-ball fine
pitch Ball Grid Array, and 256-ball Ball Grid Array
x Industrial temperature range (–40°C to +85°C) is available
for selected speeds
BB
EE
01
LL
BB
EE
10
RR
UBR
LBR
R/WR
CE0R
CE1R
OEL
I/O0L- I/O17L
Dout0-8_L
Dout9-17_L
Dout0-8_R
Dout9-17_R
128K x 18
MEMORY
ARRAY
Din_L
Din_R
OER
I/O0R - I/O17R
A16L
A0L
Address
Decoder
ADDR_L
ADDR_R
Address
Decoder
A16 R
A0R
BUSYL
SEML
INTL
CE0L
CE1L
OEL
R/WL
ARB ITR ATIO N
I NT ERRU PT
SEMAPHORE
LOGIC
M/S
TDI
TDO
JTAG
NOTES:
1. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
©2001 Integrated Device Technology, Inc.
1
OER
R/ WR
CE0 R
CE1R
TMS
TCK
TRST
BUSYR
SEM R
INTR
5621 drw 01
JUNE 2001
DSC-5621/3

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