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Integrated Device Technology - HIGH-SPEED 3.3V 64K x 16 DUAL-PORT STATIC RAM

Numéro de référence IDT70V28L20PF
Description HIGH-SPEED 3.3V 64K x 16 DUAL-PORT STATIC RAM
Fabricant Integrated Device Technology 
Logo Integrated Device Technology 





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IDT70V28L20PF fiche technique
HIGH-SPEED 3.3V
64K x 16 DUAL-PORT
STATIC RAM
IDT70V28L
.eatures
x True Dual-Ported memory cells which allow simultaneous
access of the same memory location
x High-speed access
– Commercial: 15/20ns (max.)
– Industrial: 20ns (max.)
x Low-power operation
– IDT70V28L
Active: 440mW (typ.)
Standby: 660µW (typ.)
x Dual chip enables allow for depth expansion without
external logic
x IDT70V28 easily expands data bus width to 32 bits or
more using the Master/Slave select when cascading more
than one device
.unctional Block Diagram
R/WL
UBL
CE0L
CE1L
OEL
LBL
x M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
x Busy and Interrupt Flags
x On-chip port arbitration logic
x Full on-chip hardware support of semaphore signaling
between ports
x Fully asynchronous operation from either port
x Separate upper-byte and lower-byte controls for multi-
plexed bus and bus matching compatibility
x LVTTL-compatible, single 3.3V (±0.3V) power supply
x Available in a 100-pin TQFP
x Industrial temperature range (–40°C to +85°C) is available
for selected speeds
R/WR
UBR
CE0R
CE1R
OER
LBR
I/O 8-15L
I/O 0-7L
BUSYL (1,2)
I/O
Control
I/O
Control
A15L
A0L
Address
Decoder
16
CE0L
CE1L
OEL
R/WL
64Kx16
MEMORY
ARRAY
70V28
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
16
SEML
INT
(2)
L
NOTES:
M/S(1)
1. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
©2002 Integrated Device Technology, Inc.
1
Address
Decoder
I/O8-15R
I/O0-7R
BUSYR (1,2)
A15R
A0R
CE0R
CE1R
OER
R/WR
SEMR
INTR (2)
4849 drw 01
JANUARY 2002
DSC-4849/3

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