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PDF IDT70V24 Data sheet ( Hoja de datos )
| Número de pieza | IDT70V24 | |
| Descripción | HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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Integrated Device Technology, Inc.
HIGH-SPEED 3.3V
4K x 16 DUAL-PORT
STATIC RAM
IDT70V24S/L
FEATURES:
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• High-speed access
— Commercial: 25/35/55ns (max.)
• Low-power operation
— IDT70V24S
Active: 230mW (typ.)
Standby: 3.3mW (typ.)
— IDT70V24L
Active: 230mW (typ.)
Standby: .66mW (typ.)
• Separate upper-byte and lower-byte control for
multiplexed bus compatibility
• IDT70V24 easily expands data bus width to 32 bits or
more using the Master/Slave select when cascading
more than one device
• M/S = H for BUSY output flag on Master
M/S = L for BUSY input on Slave
• Busy and Interrupt Flags
• Devices are capable of withstanding greater than 2001V
electrostatic charge.
• On-chip port arbitration logic
• Full on-chip hardware support of semaphore signaling
between ports
• Fully asynchronous operation from either port
• LVTTL-compatible, single 3.3V (±0.3V) power supply
• Available in 84-pin PGA, 84-pin PLCC, and 100-pin
TQFP
DESCRIPTION:
The IDT70V24 is a high-speed 4K x 16 Dual-Port Static
RAM. The IDT70V24 is designed to be used as a stand-alone
64K-bit Dual-Port RAM or as a combination MASTER/SLAVE
FUNCTIONAL BLOCK DIAGRAM
R/WL
UBL
R/ WR
UBR
LBL LBR
CEL CER
OEL OER
I/O8L-I/O 15L
I/O0L-I/O 7L
BUSYL(1,2)
A11L
A0L
NOTES:
1. (MASTER):
BUSY is output;
(SLAVE): BUSY
is input.
2. BUSY outputs
and INT outputs
are non-tri-stated
push-pull.
SEML
INTL(2)
I/O
Control
I/O
Control
Address
Decoder
CEL
OEL
R/ WL
12
MEMORY
ARRAY
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
M/S
Address
Decoder
12
CER
OER
R/WR
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc.
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
6.38
I/O8R-I/O 15R
I/O0R-I/O 7R
BUSYR(1,2)
A11R
A0R
SEMR
INTR(2)
2911 drw 01
OCTOBER 1996
DSC-2911/3
1
1 page  
IDT70V24S/L
HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC = 3.3V ± 0.3V)
IDT70V24S
IDT70V24L
Symbol
|ILI|
|ILO|
Parameter
Input Leakage Current(1)
Output Leakage Current
Test Conditions
VCC = 3.6V, VIN = 0V to VCC
CE = VIH, VOUT = 0V to VCC
Min.
—
—
Max.
10
10
Min.
—
—
Max.
5
5
VOL Output Low Voltage
IOL = 4mA
— 0.4 — 0.4
VOH Output High Voltage
NOTE:
1. At Vcc ≤ 2.0V input leakages are undefined.
IOH = -4mA
2.4 — 2.4 —
Unit
µA
µA
V
V
2911 tbl 08
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1) (VCC = 3.3V ± 0.3V)
Symbol
Parameter
ICC Dynamic Operating
Current
(Both Ports Active)
Test
Condition
CE = VIL, Outputs Open
SEM = VIH
f = fMAX(3)
70V24X25
70V24X35
70V24X55
Version
Typ.(2) Max.
COM. S 80
L 80
140
120
Typ.(2) Max. Typ.(2) Max. Unit
70 115 70 115 mA
70 100 70 100
ISB1 Standby Current
(Both Ports — TTL
Level Inputs)
ISB2 Standby Current
(One Port — TTL
Level Inputs)
ISB3 Full Standby Current
(Both Ports — All
CMOS Level Inputs)
ISB4 Full Standby Current
(One Port — All
CMOS Level Inputs)
CER = CEL = VIH
SEMR = SEML = VIH
f = fMAX(3)
COM. S 12
L 10
25
20
10 25 10 25 mA
8 20 8 20
CE CE"A"=VIL and "B"=VIH(5) COM. S 40
82
35 72 35 72 mA
Active Port Outputs Open
f = fMAX(3)
SEMR = SEML = VIH
L 40 72 35 62 35 62
Both Ports CEL and
CER >VCC - 0.2V
COM. S 1.0
5
1.0 5 1.0 5 mA
L 0.2 2.5 0.2 2.5 0.2 2.5
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(4)
SEMR = SEML > VCC-0.2V
CE"A" < 0.2 and
COM. S 50
CE"B" > VCC - 0.2V(5)
L 50
SEMR = SEML > VCC-0.2V
VIN > VCC - 0.2V or
VIN < 0.2V, Active Port
Outputs Open,
f = fMAX(3)
81
71
45 71 45 71 mA
45 61 45 61
NOTES:
2911 tbl 09
1. "X" in part numbers indicates power rating (S or L).
2. VCC = 3.3V, TA = +25°C, and are not production tested. ICC DC = 70mA (typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ tRC, and using “AC Test Conditions”
of input levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6.38 5
5 Page 
IDT70V24S/L
HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM
TIMING WAVEFORM OF SLAVE WRITE (M/S = VIH)
WR/ "A"
BUSY"B"
tWP
tWB( 3 )
COMMERCIAL TEMPERATURE RANGE
tWH ( 1 )
WR/ "B"
(2)
NOTES:
1. tWH must be met for both BUSY input (slave) and output (master).
2. Busy is asserted on port "B" Blocking R/W"B", until BUSY"B" goes High.
3. tWB is only for the "slave" version.
2911 drw 13
WAVEFORM OF BUSY ARBITRATION CONTROLLED BY CE TIMING(M/S = VIH)(1)
ADDR"A"
and "B"
ADDRESSES MATCH
CE"A"
CE"B"
BUSY"B"
tAPS(2)
tBAC
tBDC
2911 drw 14
WAVEFORM OF BUSY ARBITRATION CYCLE CONTROLLED BY ADDRESS MATCH TIMING
(M/S = VIH)(1)
ADDR"A"
ADDR"B"
BUSY"B"
tAPS (2)
ADDRESS "N"
MATCHING ADDRESS "N"
tBAA
tBDA
2911 drw 15
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. If tAPS is not satisfied, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted.
6.38
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11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet IDT70V24.PDF ] | |
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