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IDT70T25 fiches techniques PDF

Integrated Device Technology - HIGH-SPEED 2.5V 8/4K x 18 DUAL-PORT 8/4K x 16 DUAL-PORT STATIC RAM

Numéro de référence IDT70T25
Description HIGH-SPEED 2.5V 8/4K x 18 DUAL-PORT 8/4K x 16 DUAL-PORT STATIC RAM
Fabricant Integrated Device Technology 
Logo Integrated Device Technology 





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IDT70T25 fiche technique
HIGH-SPEED 2.5V
8/4K x 18 DUAL-PORT
8/4K x 16 DUAL-PORT
STATIC RAM
PRELIMINARY
IDT70T35/34L
IDT70T25/24L
Features
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
IDT70T35/34L (IDT70T25/24L)
– Commercial: 20/25ns (max.)
– Industrial: 25ns (max.)
Low-power operation
– IDT70T35/34L (IDT70T25/24L)
Active: 200mW (typ.)
Standby: 600µW (typ.)
Separate upper-byte and lower-byte control for multiplexed
bus compatibility
IDT70T35/34L (IDT70T25/24L) easily expands data bus
width to 36 bits (32 bits) or more using the Master/Slave
select when cascading more than one device
M/S = VIH for BUSY output flag on Master
M/S = VIL for BUSY input on Slave
BUSY and Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
LVTTL-compatible, single 2.5V (±100mV) power supply
Available in a 100-pin Thin Quad Flatpack (TQFP) package
and 100-pin fine pitch Ball Grid Array (fpBGA)
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Functional Block Diagram
R/WL
UBL
R/WR
UBR
LBL
CEL
OEL
LBR
CER
OER
I/O9L-I/O17L(5)
I/O0L-I/O8L(4)
BUSYL(2,3)
A12L(1)
A0L
I/O
Control
I/O
Control
Address
Decoder
13
CEL
OEL
R/WL
MEMORY
ARRAY
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
13
SEML
INTL(3)
NOTES:
1. A12 is a NC for IDT70T34 and IDT70T24.
2. (MASTER): BUSY is output; (SLAVE): BUSY is input.
3. BUSY outputs and INT outputs are non-tri-stated push-pull.
4. I/O0x - I/O7x for IDT70T25/24.
5. I/O8x - I/O15x for IDT70T25/24.
©2002 Integrated Device Technology, Inc.
M/S
1
Address
Decoder
CER
OER
R/WR
,
I/O9R-I/O17R(5)
I/O0R-I/O8R(4)
BUSYR(2,3)
A12R(1)
A0R
SEMR
INTR(3)
5639 drw 01
DECEMBER 2002
DSC-5639/2

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