IDT74FCT163501APA Datasheet PDF - Integrated Device Technology
| Part Number | IDT74FCT163501APA | |
| Description | 3.3V CMOS 18-BIT REGISTERED TRANSCEIVER | |
| Manufacturers | Integrated Device Technology | |
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Integrated Device Technology, Inc.
3.3V CMOS
18-BIT REGISTERED
TRANSCEIVER
IDT74FCT163501/A/C
FEATURES:
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
• Packages include 25 mil pitch SSOP, 19.6 mil pitch
TSSOP and 15.7 mil pitch TVSOP
• Extended commercial range of -40°C to +85°C
• VCC = 3.3V ±0.3V, Normal Range or
VCC = 2.7 to 3.6V, Extended Range
• CMOS power levels (0.4µW typ. static)
• Rail-to-Rail output swing for increased noise margin
• Low Ground Bounce (0.3V typ.)
• Inputs (except I/O) can be driven by 3.3V or 5V
components
DESCRIPTION:
The FCT163501/A/C 18-bit registered transceivers are
built using advanced dual metal CMOS technology. These
high-speed, low-power 18-bit registered bus transceivers
combine D-type latches and D-type flip-flops to allow data flow
in transparent, latched and clocked modes. Data flow in each
direction is controlled by output-enable (OEAB and OEBA),
latch enable (LEAB and LEBA) and clock (CLKAB and CLKBA)
inputs. For A-to-B data flow, the device operates in transpar-
ent mode when LEAB is HIGH. When LEAB is LOW, the A
data is latched if CLKAB is held at a HIGH or LOW logic level.
If LEAB is LOW, the A bus data is stored in the latch/flip-flop
on the LOW-to-HIGH transition of CLKAB. OEAB performs
the output enable function on the B port. Data flow from B port
to A port is similiar but requires using OEBA, LEBA and
CLKBA. Flow-through organization of signal pins simplifies
layout. All inputs are designed with hysteresis for improved
noise margin.
The FCT163501/A/C have series current limiting resistors.
These offer low ground bounce, minimal undershoot, and
controlled output fall times-reducing the need for external
series terminating resistors.
FUNCTIONAL BLOCK DIAGRAM
OEAB
CLKBA
LEBA
OEBA
CLKAB
LEAB
A1
CC
DD
CC
DD
B1
TO 17 OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc.
8.6
2776 drw 01
AUGUST 1996
DSC-2776/4
1
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IDT74FCT163501/A/C
3.3V 18-BIT REGISTERED TRANSCEIVER
COMMERCIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE(4)
FCT163501
FCT163501A
FCT163501C
Symbol
Parameter
Condition(1)
fMAX CLKAB or CLKBA frequency CL = 50pF
Min.(2)
—
Max.
100
Min.(2)
—
Max.
150
Min.(2)
—
Max.
150
Unit
MHz
tPLH Propagation Delay
RL = 500Ω
1.5
6.5
1.5
5.1
1.5
4.6 ns
tPHL Ax to Bx or Bx to Ax
tPLH Propagation Delay
1.5 7.5 1.5 5.6 1.5 5.3 ns
tPHL LEBA to Ax, LEAB to Bx
tPLH Propagation Delay
1.5 8.0 1.5 5.6 1.5 5.3 ns
tPHL CLKBA to Ax, CLKAB to Bx
tPZH Output Enable Time
tPZL OEBA to Ax, OEAB to Bx
1.5 8.0 1.5 6.0 1.5 5.6 ns
tPHZ Output Disable Time
tPLZ OEBA to Ax, OEAB to Bx
1.5 7.5 1.5 5.6 1.5 5.2 ns
tSU Set-up Time, HIGH or LOW
4.0 — 3.0 — 3.0 — ns
Ax to CLKAB, Bx to CLKBA
tH Hold Time, HIGH or LOW
0 — 0 — 0 — ns
Ax to CLKAB, Bx to CLKBA
tSU Set-up Time Clock
4.0 — 3.0 — 3.0 — ns
HIGH or LOW LOW
Ax to LEAB, Clock
1.5 — 1.5 — 1.5 — ns
Bx to LEBA HIGH
tH Hold Time HIGH or LOW
1.5 — 1.5 — 1.5 — ns
Ax to LEAB, Bx to LEBA
tW LEAB or LEBA Pulse Width
HIGH(5)
3.0 — 3.0 — 3.0 — ns
tW CLKAB or CLKBA Pulse
Width HIGH or LOW(5)
3.0 — 3.0 — 3.0 — ns
tSK(o) Output Skew(3)
— 0.5 — 0.5 — 0.5 ns
NOTES:
2776 tbl 07
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
4. Propagation Delays and Enable/Disable times are with VCC = 3.3V ±0.3V, Normal Range. For VCC = 2.7V to 3.6V, Extended Range, all Propagation Delays
and Enable/Disable times should be degraded by 20%.
5. This parameter is guaranteed but not tested.
8.6 5
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