IDT74FCT163374PA Datasheet PDF - Integrated Device Technology
| Part Number | IDT74FCT163374PA | |
| Description | 3.3V CMOS 16-BIT REGISTER (3-STATE) | |
| Manufacturers | Integrated Device Technology | |
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Integrated Device Technology, Inc.
3.3V CMOS
16-BIT REGISTER
(3-STATE)
IDT74FCT163374/A/C
FEATURES:
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
• Packages include 25 mil pitch SSOP, 19.6 mil pitch
TSSOP and 15.7 mil pitch TVSOP
• Extended commercial range of -40°C to +85°C
• VCC = 3.3V ±0.3V, Normal Range or
VCC = 2.7 to 3.6V, Extended Range
• CMOS power levels (0.4µW typ. static)
• Rail-to-Rail output swing for increased noise margin
• Low Ground Bounce (0.3V typ.)
• Inputs (except I/O) can be driven by 3.3V or 5V
components
DESCRIPTION:
The FCT163374/A/C 16-bit edge-triggered D-type regis-
ters are built using advanced dual metal CMOS technology.
These high-speed, low-power registers are ideal for use as
buffer registers for data synchronization and storage. The
Output Enable (xOE) and clock (xCLK) controls are organized
to operate each device as two 8-bit registers or one 16-bit
register with common clock. Flow-through organization of
signal pins facilitates ease of layout. All inputs are designed
with hysteresis for improved noise margin.
The inputs of FCT163374/A/C can be driven from either
3.3V or 5V devices. This feature allows the use of these
devices as translators in a mixed 3.3V/5V supply system.
FUNCTIONAL BLOCK DIAGRAM
1OE
1CLK
1D1
D
C
2OE
2CLK
2D1
1O1
D
C
2O1
TO 7 OTHER CHANNELS
2775 drw 01
TO 7 OTHER CHANNELS
2775 drw 02
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc.
8.5
AUGUST 1996
DSC-4637/5
1
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IDT74FCT163374/A/C
3.3V 16-BIT REGISTER (3-STATE)
COMMERCIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE(4)
FCT163374
FCT163374A
FCT163374C
Symbol
Parameter
Condition(1)
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max. Unit
tPLH Propagation Delay
tPHL xCLK to xOx
CL = 50pF
2.0
10.0
2.0
6.5
2.0
5.2 ns
RL = 500Ω
tPZH Output Enable Time
1.5 12.5 1.5 6.5 1.5 5.5 ns
tPZL
tPHZ Output Disable Time
1.5 8.0 1.5 5.5 1.5 5.0 ns
tPLZ
tSU Set-up Time HIGH
2.0 — 2.0 — 2.0 — ns
or LOW, xDx to xCLK
tH Hold Time HIGH
1.5 — 1.5 — 1.5 — ns
or LOW, xDx to xCLK
tW xCLK Pulse Width
7.0 — 5.0 — 5.0 — ns
HIGH or LOW
tSK(o) Output Skew(3)
— 0.5 — 0.5 — 0.5 ns
NOTES:
2775 tbl 08
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
4. Propagation Delay and Enable/Disable times are with VCC = 3.3V ±0.3V, Normal Range. For VCC = 2.7V to 3.6V, Extended Range, all Propagation Delays
and Enable/Disable times should be degraded by 20%.
8.5 5
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for IDT74FCT163374PA electronic component. |
| Information | Total 7 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ IDT74FCT163374PA.PDF Datasheet ] | |
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