IDT72825LB20BG Datasheet PDF - Integrated Device Technology
| Part Number | IDT72825LB20BG | |
| Description | CMOS DUAL SyncFIFO DUAL 256 x 18/ DUAL 512 x 18/ DUAL 1024 x 18 | |
| Manufacturers | Integrated Device Technology | |
| Logo |  |
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Integrated Device Technology, Inc.
CMOS DUAL SyncFIFO™
DUAL 256 x 18, DUAL 512 x 18,
DUAL 1024 x 18
IDT72805LB
IDT72815LB
IDT72825LB
FEATURES:
• The 72805 is equivalent to two 72205LB 256 x 18
FIFOs
• The 72815 is equivalent to two 72215LB 512 x 18
FIFOs
• The 72825 is equivalent to two 72225LB 1024 x 18
FIFOs
• Offers optimal combination of large capacity (2K), high
speed, design flexibility, and small footprint
• Ideal for the following applications:
- Network switching
- Two level prioritization of parallel data
- Bidirectional data transfer
- Busmatching between 18-bit and 36-bit data paths
- Width expansion to 36-bit per package
- Depth expansion to 2048 words per package
• 20ns read/write cycle time, 12ns access time
• Read and write clocks can be asynchronous or coinci-
dent (permits simultaneous reading and writing of data
on a single clock edge)
• Programmable almost-empty and almost-full flags
• Empty and Full flags signal FIFO status
• Half-Full flag capability in single device configuration
• Enable puts output data bus in high impedance state
• High-performance submicron CMOS technology
• Available in a 121-lead, 16 x 16 mm plastic Ball Grid
Array (BGA)
• Industrial temperature range (-40oC to +85oC) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT72805LB/72815LB/72825LB are dual 18-bit-wide
synchronous (clocked) first-in, first-out (FIFO) memories.
These devices are functionally equivalent to two IDT72205LB/
72215LB/72225LB FIFOs in a single package with all associ-
ated control, data, and flag lines assigned to independent
pins. These FIFOs are applicable for a wide variety of data
buffering needs, such as optical disk controllers, local area
networks (LANs), and interprocessor communication.
Each of the two FIFOs contained in the IDT72805LB/
72815LB/72825LB has an 18-bit input data port (D0 - D17)
and an 18-bit output data port (Q0 - Q17). Each input port is
controlled by a free-running Write Clock (WCLK) and a data
input Write Enable pin (WEN). Data is written into each array
on every rising clock edge of the appropriate Write Clock
(WCLK) when its corresponding Write Enable line (WEN) is
asserted.
FUNCTIONAL BLOCK DIAGRAM
WCLKA
WENA
DA0-DA17
FFA
HFA/(WXOA)
PAEA
EFA
LDA PAFA
WCLKB
WENB
DB0-DB17
LDB
••
INPUT
REGISTER
OFFSET
REGISTER
WRITE
CONTROL
LOGIC
FLA
WXIA
(HFA)/WXOA
RXIA
RXOA
WRITE
POINTER
EXPANSION
LOGIC
RSA
RESET
LOGIC
••
RAM
ARRAY
256 x 18
512 x 18
1024 x 18
••
OUTPUT
REGISTER
FLAG
LOGIC
READ
POINTER
READ
CONTROL
LOGIC
••
••
INPUT
REGISTER
WRITE
CONTROL
LOGIC
WRITE
POINTER
•
•
RAM
ARRAY
256 x 18
512 x 18
1024 x 18
••
EXPANSION
LOGIC
RESET
LOGIC
OUTPUT
REGISTER
OFFSET
REGISTER
FLAG
LOGIC
READ
POINTER
READ
CONTROL
LOGIC
••
FFB
PAFB
EPAFBEB
HFB/
(WXOB)
OEA QA0-QA17
RCLKA
RENA
RSB
RXOB
RXIB
(HFB)/WXOB
WXIB
FLB
OEB
QB0-QB17
The IDT logo is a registered trademark, and SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-839
5.17
RCLKB
RENB
3139 drw 01
DECEMBER 1996
DSC-3139/2
1
|
| |
 
IDT72805/72815/72825 CMOS Dual SyncFIFO™
256 x 18-BIT, 512 x 18, and 1024 x 18
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C)
Symbol Parameter
fS
tA
tCLK
tCLKH
tCLKL
tDS
tDH
tENS
tENH
tRS
tRSS
tRSR
tRSF
tOLZ
tOE
tOHZ
tWFF
tREF
tPAF
tPAE
tHF
tXO
tXI
tXIS
tSKEW1
tSKEW2
Clock Cycle Frequency
Data Access Time
Clock Cycle Time
Clock HIGH Time
Clock LOW Time
Data Set-up Time
Data Hold Time
Enable Set-up Time
Enable Hold Time
Reset Pulse Width(1)
Reset Set-up Time
Reset Recovery Time
Reset to Flag and Output Time
Output Enable to Output in Low-Z(2)
Output Enable to Output Valid
Output Enable to Output in High-Z(2)
Write Clock to Full Flag
Read Clock to Empty Flag
Clock to Programmable Almost-Full Flag
Clock to Programmable Almost-Empty Flag
Clock to Half-Full Flag
Clock to Expansion Out
Expansion In Pulse Width
Expansion In Set-Up Time
Skew time between Read Clock & Write Clock for
Full Flag
Skew time between Read Clock & Write Clock for
Empty Flag
NOTES:
1. Pulse widths less than minimum values are not allowed.
2. Values guaranteed by design, not currently tested.
COMMERCIAL TEMPERATURE RANGE
72805LB20
72815LB20
72825LB20
Min. Max.
— 50
2 12
20 —
8—
8—
5—
1—
5—
1—
20 —
12 —
12 —
— 35
0—
—9
19
— 12
— 12
— 30
— 30
— 30
— 12
8—
8—
14 —
Commercial
72805LB25
72815LB25
72825LB25
Min. Max.
— 40
3 15
25 —
10 —
10 —
6—
1—
6—
1—
25 —
15 —
15 —
— 40
0—
— 12
1 12
— 15
— 15
— 35
— 35
— 35
— 15
10 —
10 —
16 —
72805LB35
72815LB35
72825LB35
Min. Max.
— 28.6
3 20
35 —
14 —
14 —
7—
2—
7—
2—
35 —
20 —
20 —
— 45
0—
— 15
1 15
— 20
— 20
— 40
— 40
— 40
— 20
14 —
15 —
18 —
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
14 — 16 — 18 — ns
3139 tbl 06
5V
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
1.1K
GND to 3.0V
3ns
1.5V
1.5V
See Figure 1
3139 tbl 07
D.U.T.
680Ω
30pF*
3139 drw 05
Figure 1. Output Load
* Includes jig and scope capacitances.
5.17 5
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