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Integrated Device Technology - DUAL CMOS SyncFIFO

Numéro de référence IDT72821L12PF
Description DUAL CMOS SyncFIFO
Fabricant Integrated Device Technology 
Logo Integrated Device Technology 





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IDT72821L12PF fiche technique
DUAL CMOS SyncFIFO
Integrated Device Technology, Inc.
IDT72801
IDT72811
IDT72821
IDT72831
IDT72841
FEATURES:
• The 72801 is equivalent to two 72201 256 x 9 FIFOs
• The 72811 is equivalent to two 72211 512 x 9 FIFOs
• The 72821 is equivalent to two 72221 1024 x 9 FIFOs
• The 72831 is equivalent to two 72231 2048 x 9 FIFOs
• The 72841 is equivalent to two 72241 4096 x 9 FIFOs
• Offers optimal combination of large capacity, high speed,
design flexibility and small footprint
• Ideal for prioritization, bidirectional, and width expansion
applications
• 15 ns read/write cycle time FOR THE 72801/72811
• 20 ns read/write cycle time FOR THE 72821/72831/72841
• Separate control lines and data lines for each FIFO
• Separate empty, full, programmable almost-empty and
almost-full flags for each FIFO
• Enable puts output data lines in high-impedance state
• Space-saving 64-pin Thin Quad Flat Pack (TQFP)
• Industrial temperature range (-40OC to +85OC) is avail-
able, tested to military electrical specifications
DESCRIPTION:
72801/72811/72821/72831/72841 are dual synchronous
(clocked) FIFOs. The device is functionally equivalent to two
72201/72211/72221/72231/72241 FIFOs in a single package
with all associated control, data, and flag lines assigned to
separate pins.
Each of the two FIFOs (designated FIFO A and FIFO B)
contained in the 72801/72811/72821/72831/72841 has a 9-
bit input data port (DA0 - DA8), DB0 - DB8) and a 9-bit output
data port (QA0 - QA8, QB0 - QB8). Each input port is
controlled by a free-running clock(WCLKA, WCLKB), and two
write enable pins (WENA1, WENA2, WENB1, WENB2). Data
is written into each of the two arrays on every rising clock edge
of the write clock (WCLKA WCLKB) when the appropriate
write enable pins are asserted.
The output port of each FIFO bank is controlled by its
associated clock pin (RCLKA, RCLKB) and two read enable
pins (RENA1, RENA2, RENB1, RENB2). The read clock can
be tied to the write clock for single clock operation or the two
clocks can run asynchronous of one another for dual clock
operation. An output enable pin (OEA, OEB) is provided on the
read port of each FIFO for three-state output control .
Each of the two FIFOs has two fixed flags, empty (EFA, EFB)
and full (FFA, FFB). Two programmable flags, almost-empty
(PAEA, PAEB) and almost-full (PAFA, PAFB), are provided for
PIN CONFIGURATION
QA1
QA2
QA3
QA4
QA5
QA6
QA7
QA8
VCC
WENA2/LDA
WCLKA
WENA1
RSA
DA8
DA7
DA6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PN64-1
TQFP,
TOP VIEW
48 QB0
47 FFB
46 EFB
45 OEB
44 RENB2
43 RCLKB
42 RENB1
41 GND
40 VCC
39 PAEB
38 PAFB
37 DB0
36 DB1
35 DB2
34 DB3
33 DB4
3034 drw 01
SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
5.15
NOVEMBER 1996
DSC-3034/1
1

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