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IDT723642L20PF fiches techniques PDF

Integrated Device Technology - CMOS SyncBiFIFOO 256 x 36 x 2/ 512 x 36 x 2/ 1024 x 36 x 2

Numéro de référence IDT723642L20PF
Description CMOS SyncBiFIFOO 256 x 36 x 2/ 512 x 36 x 2/ 1024 x 36 x 2
Fabricant Integrated Device Technology 
Logo Integrated Device Technology 





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IDT723642L20PF fiche technique
Integrated Device Technology, Inc.
CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2,
1024 x 36 x 2
IDT723622
IDT723632
IDT723642
FEATURES:
• Free-running CLKA and CLKB may be asynchronous or
coincident (simultaneous reading and writing of data on a
single clock edge is permitted)
• Two independent clocked FIFOs buffering data in oppo-
site directions
• Memory storage capacity:
IDT723622–256 x 36 x 2
IDT723632–512 x 36 x 2
IDT723642–1024 x 36 x 2
• Mailbox bypass register for each FIFO
• Programmable Almost-Full and Almost-Empty flags
• Microprocessor Interface Control Logic
• IRA, ORA, AEA, and AFA flags synchronized by CLKA
• IRB, ORB, AEB, and AFB flags synchronized by CLKB
• Supports clock frequencies up to 67MHz
• Fast access times of 11ns
• Available in 132-pin Plastic Quad Flatpack (PQF) or
space-saving 120-pin Thin Quad Flatpack (PF)
• Low-power 0.8-Micron Advanced CMOS technology
• Industrial temperature range (-40oC to +85oC) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT723622/723632/723642 is a monolithic, high-speed,
low-power, CMOS Bidirectional SyncFIFO (clocked) memory
which supports clock frequencies up to 67MHz and have read
access times as fast as 11ns. Two independent 256/512/
1024x36 dual-port SRAM FIFOs on board each chip buffer
data in opposite directions. Each FIFO has flags to indicate
empty and full conditions and two programable flags (almost
FUNCTIONAL BLOCK DIAGRAM
CLKA
CSA
W/RA
ENA
MBA
Port-A
Control
Logic
RST1
FIFO1,
Mail1
Reset
Logic
36
Mail 1
Register
256 x 36
512 x 36
1024 x 36
SRAM
Write
Pointer
Read
Pointer
MBF1
36
IRA Status Flag
AFA Logic
FIFO 1
ORB
AEB
FS0
FS1
A0 - A35
ORA
AEA
Programmable Flag
Offset Registers
9
FIFO 2
Status Flag
Logic
B0 - B35
IRB
AFB
36
MBF2
Read
Pointer
Write
Pointer
256 x 36
512 x 36
1024 x 36
SRAM
Mail 2
Register
36
FIFO2,
Mail2
Reset
Logic
Port-B
Control
Logic
SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
5.22
RST2
CLKB
CSB
W/RB
ENB
MBB
3022 drw 01
DECEMBER 1996
DSC-3022/3

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