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IDT723613L15PF fiches techniques PDF

Integrated Device Technology - CMOS Clocked FIFO With Bus Matching and Byte Swapping 64 x 36

Numéro de référence IDT723613L15PF
Description CMOS Clocked FIFO With Bus Matching and Byte Swapping 64 x 36
Fabricant Integrated Device Technology 
Logo Integrated Device Technology 





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IDT723613L15PF fiche technique
Integrated Device Technology, Inc.
CMOS Clocked FIFO
With Bus Matching and Byte Swapping
64 x 36
IDT723613
FEATURES:
• Free-running CLKA and CLKB may be asynchronous or
coincident (permits simultaneous reading and writing of
data on a single clock edge)
• 64 x 36 storage capacity FIFO buffering data from Port A
to Port B
• Mailbox bypass registers in each direction
• Dynamic Port B bus sizing of 36-bits (long word), 18-bits
(word), and 9-bits (byte)
• Selection of Big- or Little-Endian format for word and byte
bus sizes
• Three modes of byte-order swapping on Port B
• Programmable Almost-Full and Almost-Empty flags
• Microprocessor interface control logic
FF, AF flags synchronized by CLKA
EF, AE flags synchronized by CLKB
• Passive parity checking on each Port
• Parity Generation can be selected for each Port
• Low-power advanced BiCMOS technology
• Supports clock frequencies up to 67 MHz
• Fast access times of 10 ns
• Available in 132-pin quad flatpack (PQF) or space-saving
120-pin thin quad flatpack (TQFP)
• Industrial temperature range (-40oC to +85oC) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT723613 is a monolithic, high-speed, low-power,
BiCMOS synchronous (clocked) FIFO memory which sup-
ports clock frequencies up to 67 MHz and has read-access
times as fast as 10 ns. The 64 x 36 dual-port SRAM FIFO
buffers data from port A to port B. The FIFO has flags to
indicate empty and full conditions, and two programmable
flags, Almost-Full (AF) and Almost-Empty (AE), to indicate
FUNCTIONAL BLOCK DIAGRAM
CLKA
CSA
W/RA
ENA
MBA
Port-A
Control
Logic
RST
ODD/
EVEN
Device
Control
36
Mail 1
Register
64 x 36
SRAM
Parity
Gen/Check
MBF1
PEFB
PGB
36 64 x 36
Write
Pointer
Read
Pointer
B0 - B35
FF
AF
FS0
FS1
A0 - A35
PGA
PEFA
MBF2
Status Flag
Logic
FIFO
Programmable
Flag Offset
Registers
Parity
Gen/Check
Mail 2
Register
PPoorrtt--BB
CCoonnttrrooll
LLooggiicc
EF
AE
CLKB
CSB
W/RB
ENB
BE
SIZ0
SIZ1
SW0
SW1
3145 drw 01
The IDT logo is a registered trademark and SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1997 Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
MAY 1997
DSC-3145/4
1

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