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PDF IDT723612L30PF Data sheet ( Hoja de datos )
| Número de pieza | IDT723612L30PF | |
| Descripción | BiCMOS SyncBiFIFOO 64 x 36 x 2 | |
| Fabricantes | Integrated Device Technology | |
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BiCMOS SyncBiFIFO™
64 x 36 x 2
IDT723612
Integrated Device Technology, Inc.
FEATURES:
• Free-running CLKA and CLKB can be asynchronous or
coincident (simultaneous reading and writing of data on a
single clock edge is permitted)
• Two independent clocked FIFOs (64 x 36 storage
capacity each) buffering data in opposite directions
• Mailbox bypass Register for each FIFO
• Programmable Almost-Full and Almost-Empty Flags
• Microprocessor interface control logic
• EFA, FFA, AEA, and AFA flags synchronized by CLKA
• EFB, FFB, AEB, and AFB flags synchronized by CLKB
• Passive parity checking on each port
• Parity generation can be selected for each port
FUNCTIONAL BLOCK DIAGRAM
• Low-power advanced BiCMOS technology
• Supports clock frequencies up to 67 MHz
• Fast access times of 10ns
• Available in 132-pin plastic quad flat package (PQF) or
space-saving 120-pin thin quad flat package (TQFP)
• Industrial temperature range (-40oC to +85oC) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT723612 is a monolithic high-speed, low-power
BiCMOS bi-directional clocked FIFO memory. It supports
clock frequencies up to 67 MHz and has read access times as
CLKA
CSA
W/RA
ENA
MBA
Port-A
Control
Logic
RST
ODD/
EVEN
Device
Control
FFA
AFA
FS0
FS1
A0 - A35
EFA
AEA
36
Mail 1
Register
Parity
Gen/Check
64 x 36
SRAM
Write Read
Pointer Pointer
FIFO1
Status Flag
Logic
FIFO2
Programmable Flag
Offset Register
Status Flag
Logic
Read Write
Pointer Pointer
MBF1
PEFB
PGB
36
EFB
AEB
B0 - B36
FFB
AFB
36
64 x 36
SRAM
PGA
PEFA
MBF2
Parity
Gen/Check
Mail 2
Register
Port-B
Control
Logic
CLKB
CSB
W/RB
ENB
MBB
The IDT logo is a registered trademark and Sync BiFIFO is a trademark of Integrated Device Technology Inc.
COMMERCIAL TEMPERATURE RANGE
©1997 Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
3136 drw 01
MAY 1997
DSC-3136/4
1
1 page  
IDT723612 BiCMOS SyncBiFIFO™
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION (CONTINUED)
SYMBOL NAME
I/O
DESCRIPTION
MBB
MBF1
MBF2
ODD/
EVEN
PEFA
PEFB
PGA
PGB
RST
W/RA
W/RB
Port-B Mailbox
Select
Mail1 Register Flag
Mail2 Register Flag
Odd/Even Parity
Select
Port-A Parity Error
Flag
Port-B Parity Error
Flag
Port-A Parity
Port-B Parity
Generation
Reset
Port-A Write/Read
Select
Port-B Write/Read
Select
I A HIGH level on MBB chooses a mailbox register for a port-B read or write
operation. When the B0-B35 outputs are active, a HIGH level on MBB selects
data from the mail1 register for output, and a LOW level selects FIFO1
output register data for output.
O MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to
the mail1 register. Writes to the mail1 register are inhibited while MBF1 is set
LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when a port-
B read is selected and MBB is HIGH. MBF1 is set HIGH when the device is
reset.
O MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to
the mail2 register. Writes to the mail2 register are inhibited while MBF2 is set
LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a port-
A read is selected and MBA is HIGH. MBF2 is set HIGH when the device is
reset.
I Odd parity is checked on each port when ODD/EVEN is HIGH, and even
parity is checked when ODD/EVEN is LOW. ODD/EVEN also selects the
type of parity generated for each port if parity generation is enabled for a read
operation.
O When any byte applied to terminals A0-A35 fails parity, PEFA is LOW.
(Port A) Bytes are organized as A0-A8, A9-A17, A18-A26, and A27-A35, with the
most significant bit of each byte serving as the parity bit. The type of parity
checked is determined by the state of the ODD/EVEN input. The parity trees
used to check the A0-A35 inputs are shared by the mail2 register to generate
parity if parity generation is selected by PGA. Therefore, if a mail2 read with
parity generation is setup by having W/RA LOW, MBA HIGH, and PGA HIGH,
the PEFA flag is forcedHIGH regardless of the A0-A35 inputs.
O When any byte applied to terminals B0-B35 fails parity, PEFB is LOW.
(Port B) Bytes are organized as B0-B8, B9-B17, B18-B26, B27-B35 with the most
significant bit of each byte serving as the parity bit. The type of parity
checked is determined by the state of the ODD/EVEN input. The parity trees
used to check the B0-B35 inputs are shared by the mail1 register to generate
parity if parity generation is selected by PGB. Therefore, if a mail1 read with
parity generation is setup by having W/RB LOW, MBB HIGH, and PGB HIGH,
the PEFB flag is forced HIGH regardless of the state of the B0-B35 inputs.
I Parity is generated for data reads from port A when PGA is HIGH. Genera-
tion The type of parity generated is selected by the state of the ODD/EVEN
input. Bytes are organized as A0-A8, A9-A17, A18-A26, and A27-A35. The
generated parity bits are output in the most significant bit of each byte.
I Parity is generated for data reads from port B when PGB s HIGH. The type of
parity generated is selected by the state of the ODD/EVEN input. Bytes are
organized as B0-B8, B9-B17, B18-B26, and B27-B35. The generated parity
bits are output in the most significant bit of each byte.
I To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-to-
HIGH transitions of CLKB must occur while RST is LOW. This sets the AFA,
AFB, MBF1, and MBF2 flags HIGH and the EFA, EFB, AEA, AEB, FFA, and
FFB flags LOW. The LOW-to-HIGH transition of RST latches the status of the
FS1 and FS0 inouts to select almost-full and almost-empty flag offset.
I A HIGH selects a write operation and a LOW selects a read operation on
port A for a LOW-to-HIGH transition of CLKA. The A0-A35 outputs are in the
high-impedance state when W/RA is HIGH.
I A HIGH selects a write operation and a LOW selects a read operation on
port B for a LOW-to-HIGH transition of CLKB. The B0-B35 outputs are in the
high-impedance state when W/RB is HIGH.
5
5 Page 
IDT723612 BiCMOS SyncBiFIFO™
64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
X or less words in memory and is HIGH when the FIFO
contains (X+1) or more words.
Two LOW-to-HIGH transitions of the almost-empty flag
synchronizing clocks are required after a FIFO write for the
almost-empty flag to reflect the new level of fill. Therefore, the
almost-empty flag of a FIFO containing (X+1) or more words
remains LOW if two cycles of the synchronizing clock have not
elapsed since the write that filled the memory to the (X+1)
level. An almost-empty flag is set HIGH by the second LOW-
to-HIGH transition of the synchronizing clock after the FIFO
write that fills memory to the (X+1) level. A LOW-to-HIGH
transition of an almost-empty flag synchronizing clock begins
the first synchronization cycle if it occurs at time tSKEW2 or
greater after the write that fills the FIFO to (X+1) words.
Otherwise, the subsequent synchronizing clock cycle can be
the first synchronization cycle (see Figure 6 and 7).
ALMOST FULL FLAGS (AFA, AFB)
The almost-full flag of a FIFO is synchronized to the port
clock that writes data to its array. The state machine that
controls an almost-full flag monitors a write-pointer and read-
pointer comparator that indicates when the FIFO SRAM
status is almost full, almost full-1, or almost full-2. The almost-
full state is defined by the value of the almost-full and almost-
empty offset register (X). This register is loaded with one of
four preset values during a device reset (see Reset above).
An almost-full flag is LOW when the FIFO contains (64-X) or
more words in memory and is HIGH when the FIFO contains
[64-(X+1)] or less words.
Two LOW-to-HIGH transitions of the almost-full flag
synchronizing clock are required after a FIFO read for the
almost-full flag to reflect the new level of fill. Therefore, the
almost-full flag of a FIFO containing [64-(X+1)]or less words
remains LOW if two cycles of the synchronizing clock have not
elapsed since the read that reduced the number of words in
memory to [64-(X+1)]. An almost-full flag is set HIGH by the
second LOW-to-HIGH transition of the synchronizing clock
after the FIFO read that reduces the number of words in
memory to [64-(X+1)]. A second LOW-to-HIGH transition of
an almost-full flag synchronizing clock begins the first syn-
chronization cycle if it occurs at time tSKEW2 or greater after the
read that reduces the number of words in memory to [64-
(X+1)]. Otherwise, the subsequent synchronizing clock cycle
can be the first synchronization cycle (see Figure 13 and 14).
MAILBOX REGISTERS
Each FIFO has a 36-bit bypass register to pass command
and control information between port A and port B without
putting it in queue. The mailbox-select (MBA, MBB) inputs
choose between a mail register and a FIFO for a port data
transfer operation. A LOW-to-HIGH transition on CLKA writes
A0-A35 data to the mail1 register when a port-A write is
selected by CSA, W/RA, and ENA and MBA HIGH. A LOW-
to-HIGH transition on CLKB writes B0-B35 data to the mail2
register when a port-B write is selected by CSB, W/RB, and
ENB and MBB is HIGH. Writing data to a mail register sets the
corresponding flag (MBF1 or MBF2) LOW. Attempted writes
to a mail register are ignored while the mail flag is LOW.
When a port's data outputs are active, the data on the bus
comes from the FIFO output register when the port mailbox-
select input (MBA, MBB) is LOW and from the mail register
when the port mailbox-select input is HIGH. The mail1 register
flag (MBF1) is set HIGH by a LOW-to-HIGH transition on
CLKB when a port-B read is selected by CSB, W/RB, and ENB
and MBB is HIGH. The mail2 register flag (MBF2) is set HIGH
by a LOW-to-HIGH transition on CLKA when port-A read is
selected by CSA, W/RA, and ENA and MBA is HIGH. The data
in a mail register remains intact after it is read and changes
only when new data is written to the register.
PARITY CHECKING
The port-A inputs (A0-A35) and port-B inputs (B0-B35)
each have four parity trees to check the parity of incoming (or
outgoing) data. A parity failure on one or more bytes of the
input bus is reported by a LOW level on the port parity error flag
(PEFA, PEFB). Odd or even parity checking can be selected,
and the parity error flags can be ignored if this feature is not
desired.
Parity status is checked on each input bus according to
the level of the odd/even parity (ODD/EVEN) select input. A
parity error on one or more bytes of a port is reported by a LOW
level on the corresponding port parity error flag (PEFA, PEFB)
output. Port-A bytes are arranged as A0-A8, A9-A17, A18-
A26, and A27-A35 with the most significant bit of each byte
used as the parity bit. Port-B bytes are arranged as B0-B8, B9-
B17, B18-B26, and B27-B35, with the most significant bit of
each byte used as the parity bit. When odd/even parity is
selected, a port parity error flag (PEFA, PEFB) is LOW if any
byte on the port has an odd/even number of LOW levels
applied to the bits.
The four parity trees used to check the A0-A35 inputs are
shared by the mail2 register when parity generation is se-
lected for port-A reads (PGA = HIGH). When a port-A read
from the mail2 register with parity generation is selected with
W/RA LOW, CSA LOW, ENA HIGH, MBA HIGH, and PGA
HIGH, the port-A parity error flag (PEFA) is held HIGH regard-
less of the levels applied to the A0-A35 inputs. Likewise, the
parity trees used to check the B0-B35 inputs are shared by the
mail1 register when parity generation is selected for port-B
reads (PGB = HIGH). When a port-B read from the mail1
register with parity generation is selected with W/RB LOW,
CSB LOW, ENB HIGH, MBB HIGH, and PGB HIGH, the port-
B parity error flag (PEFB) is held HIGH regardless of the levels
applied to the B0-B35 inputs.
PARITY GENERATION
A HIGH level on the port-A parity generate select (PGA)
or port-B parity generate select (PGB) enables the IDT723612
to generate parity bits for port reads from a FIFO or mailbox
register. Port-A bytes are arranged as A0-A8, A9-A17, A18-
26, and A27-A35, with the most significant bit of each byte
used as the parity bit. Port-B bytes are arranged as B0-B8, B9-
B17, B18-B26, and B27-B35, with the most significant bit of
each byte used as the parity bit. A write to a FIFO or mail
register stores the levels applied to all thirty-six inputs regard-
less of the state of the parity generate select (PGA, PGB)
11
11 Page | ||
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| PDF Descargar | [ Datasheet IDT723612L30PF.PDF ] | |
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