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PDF IDT72251 Data sheet ( Hoja de datos )
| Número de pieza | IDT72251 | |
| Descripción | CMOS SyncFIFOO 8192 X 9 | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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Integrated Device Technology, Inc.
CMOS SyncFIFO™
8192 X 9
ADVANCED
INFORMATION
IDT72251
FEATURES:
• 8192 x 9-bit organization
• Pin/function compatible with IDT72421/722x1 family
• 15 ns read/write cycle time
• Read and write clocks can be independent
• Dual-Ported zero fall-through time architecture
• Empty and Full flags signal FIFO status
• Programmable Almost-Empty and Almost-Full flags can
be set to any depth
• Programmable Almost-Empty and Almost-Full flags
default to Empty+7, and Full-7, respectively
• Output enable puts output data bus in high-impedance
state
• Advanced submicron CMOS technology
• Available in 32-pin plastic leaded chip carrier (PLCC)
• Industrial temperature range (-40oC to +85oC) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT72251 SyncFIFO™ is a very high-speed, low-
power First-In, First-Out (FIFO) memory with clocked read
and write controls. The IDT72251 has a 8192 x 9-bit memory
array. This FIFO is applicable for a wide variety of data
buffering needs such as graphics, local area networks and
interprocessor communication.
This FIFO has a 9-bit input and output port. The input port
is controlled by a free-running clock (WCLK), and two write
enable pins (WEN1, WEN2). Data is written into the
Synchronous FIFO on every rising clock edge when the write
enable pins are asserted. The output port is controlled by
another clock pin (RCLK) and two read enable pins (REN1,
REN2). The read clock can be tied to the write clock for single
clock operation or the two clocks can run asynchronous of one
another for dual-clock operation. An output enable pin (OE) is
provided on the read port for three-state control of the output.
The Synchronous FIFO has two fixed flags, Empty (EF) and
Full (FF). Two programmable flags, Almost-Empty (PAE) and
Almost-Full (PAF), are provided for improved system control.
The programmable flags default to Empty+7 and Full-7 for
PAE and PAF, respectively. The programmable flag offset
loading is controlled by a simple state machine and is initiated
by asserting the load pin (LD).
The IDT72251 is fabricated using IDT’s high-speed
submicron CMOS technology.
FUNCTIONAL BLOCK DIAGRAM
WCLK
WEN2
WRITE CONTROL
LOGIC
D0 - D8
INPUT REGISTER
OFFSET REGISTER
FLAG
LOGIC
WRITE POINTER
RAM ARRAY
8192 x 9
READ POINTER
READ CONTROL
LOGIC
RESET LOGIC
OUTPUT REGISTER
RCLK
Q0 - Q8
SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
5.14
3545 drw 01
DECEMBER 1996
DSC-3545/-
1
1 page  
IDT72251 CMOS SyncFIFO™
8192 x 9
COMMERCIAL TEMPERATURE RANGES
SIGNAL DESCRIPTIONS
INPUTS:
Data In (D0 - D8) — Data inputs for 9-bit wide data.
CONTROLS:
Reset (RS) — Reset is accomplished whenever the Reset
(RS) input is taken to a LOW state. During reset, both internal
read and write pointers are set to the first location. A reset is
required after power-up before a write operation can take
place. The Full Flag (FF) and Programmable Almost-Full Flag
(PAF) will be reset to HIGH after tRSF. The Empty Flag (EF) and
Programmable Almost-Empty Flag (PAE) will be reset to LOW
after tRSF. During reset, the output register is initialized to all
zeros and the offset registers are initialized to their default
values.
Write Clock (WCLK) — A write cycle is initiated on the
LOW-to-HIGH transition of the write clock (WCLK). Data set-
up and hold times must be met in respect to the LOW-to-HIGH
transition of the write clock (WCLK). The Full Flag (FF) and
Programmable Almost-Full Flag (PAF) are synchronized with
respect to the LOW-to-HIGH transition of the write clock
(WCLK).
The write and read clocks can be asynchronous or
coincident.
Write Enable 1 (WEN1) — If the FIFO is configured for
programmable flags, Write Enable 1 (WEN1) is the only
enable control pin. In this configuration, when Write Enable 1
(WEN1) is low, data can be loaded into the input register and
RAM array on the LOW-to-HIGH transition of every write clock
(WCLK). Data is stored in the RAM array sequentially and
independently of any on-going read operation.
In this configuration, when Write Enable 1 (WEN1) is HIGH,
the input register holds the previous data and no new data is
allowed to be loaded into the register.
If the FIFO is configured to have two write enables, which
allows for depth expansion, there are two enable control pins.
See Write Enable 2 paragraph below for operation in this
configuration.
To prevent data overflow, the Full Flag (FF) will go LOW,
inhibiting further write operations. Upon the completion of a
valid read cycle, the Full Flag (FF) will go HIGH after tWFF,
allowing a valid write to begin. Write Enable 1 (WEN1) is
ignored when the FIFO is full.
Read Clock (RCLK) — Data can be read on the outputs on
the LOW-to-HIGH transition of the read clock (RCLK). The
Empty Flag (EF) and Programmable Almost-Empty Flag (PAE)
are synchronized with respect to the LOW-to-HIGH transition
of the read clock (RCLK).
The write and read clocks can be asynchronous or
coincident.
Read Enables (REN1, REN2) — When both Read Enables
(REN1, REN2) are LOW, data is read from the RAM array to
the output register on the LOW-to-HIGH transition of the read
clock (RCLK).
When either Read Enable (REN1, REN2) is HIGH, the
output register holds the previous data and no new data is
allowed to be loaded into the register.
When all the data has been read from the FIFO, the Empty
Flag (EF) will go LOW, inhibiting further read operations. Once
a valid write operation has been accomplished, the Empty
Flag (EF) will go HIGH after tREF and a valid read can begin.
The Read Enables (REN1, REN2) are ignored when the FIFO
is empty.
Output Enable (OE) — When Output Enable (OE) is
enabled (LOW), the parallel output buffers receive data from
the output register. When Output Enable (OE) is disabled
(HIGH), the Q output data bus is in a high-impedance state.
Write Enable 2/Load (WEN2/LD) — This is a dual-purpose
pin. The FIFO is configured at Reset to have programmable
flags or to have two write enables, which allows depth
expansion. If Write Enable 2/Load (WEN2/LD) is set high at
Reset (RS = LOW), this pin operates as a second write enable
pin.
If the FIFO is configured to have two write enables, when
Write Enable (WEN1) is LOW and Write Enable 2/Load (WEN2/
LD) is HIGH, data can be loaded into the input register and
RAM array on the LOW-to-HIGH transition of every write clock
(WCLK). Data is stored in the RAM array sequentially and
independently of any on-going read operation.
In this configuration, when Write Enable (WEN1) is HIGH
and/or Write Enable 2/Load (WEN2/LD) is LOW, the input
register holds the previous data and no new data is allowed to
be loaded into the register.
To prevent data overflow, the Full Flag (FF) will go LOW,
inhibiting further write operations. Upon the completion of a
valid read cycle, the Full Flag (FF) will go HIGH after tWFF,
allowing a valid write to begin. Write Enable 1 (WEN1) and Write
Enable 2/Load (WEN2/LD) are ignored when the FIFO is full.
The FIFO is configured to have programmable flags when
the Write Enable 2/Load (WEN2/LD) is set LOW at Reset
(RS=low). The IDT7225 device contain four 8-bit offset
registers which can be loaded with data on the inputs, or read
on the outputs. See Figure 3 for details of the size of the
registers and the default values.
If the FIFO is configured to have programmable flags when
the Write Enable 1 (WEN1) and Write Enable 2/Load (WEN2/
LD) are set low, data on the inputs D is written into the Empty
(Least Significant Bit) offset register on the first LOW-to-HIGH
transition of the write clock (WCLK). Data is written into the
Empty (Most Significant Bit) offset register on the second
LOW-to-HIGH transition of the write clock (WCLK), into the
Full (Least Significant Bit) offset register on the third transition,
and into the Full (Most Significant Bit) offset register on the
fourth transition. The fifth transition of the write clock (WCLK)
again writes to the Empty (Least Significant Bit) offset register.
5.14 5
5 Page 
IDT72251 CMOS SyncFIFO™
8192 x 9
WCLK
NO WRITE
tSKEW1
D0 - D8
FF
tDS
tWFF
tWFF
COMMERCIAL TEMPERATURE RANGES
NO WRITE
tSKEW1
tDS
DATA WRITE
tWFF
WEN1
WEN2
(If Applicable)
RCLK
REN1,
REN2
tENS
OE LOW
tENH
tA
tENS
Q0 - Q8
DATA IN OUTPUT REGISTER
DATA READ
Figure 8. Full Flag Timing
tENH
tA
NEXT DATA READ
2655 drw 10
5.14 11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet IDT72251.PDF ] | |
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