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What is IDT72220?

This electronic component, produced by the manufacturer "Integrated Device Technology", performs the same function as "CMOS SyncFIFOO 64 x 8/ 256 x 8/ 512 x 8/ 1024 x 8/ 2048 x 8 and 4096 x 8".


IDT72220 Datasheet PDF - Integrated Device Technology

Part Number IDT72220
Description CMOS SyncFIFOO 64 x 8/ 256 x 8/ 512 x 8/ 1024 x 8/ 2048 x 8 and 4096 x 8
Manufacturers Integrated Device Technology　
Logo Integrated Device Technology Logo　


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Integrated Device Technology, Inc.
CMOS SyncFIFO™
64 x 8, 256 x 8, 512 x 8,
1024 x 8, 2048 x 8 and 4096 x 8
IDT72420
IDT72200
IDT72210
IDT72220
IDT72230
IDT72240
FEATURES:
• 64 x 8-bit organization (IDT72420)
• 256 x 8-bit organization (IDT72200)
• 512 x 8-bit organization (IDT72210)
• 1024 x 8-bit organization (IDT72220)
• 2048 x 8-bit organization (IDT72230)
• 4096 x 8-bit organization (IDT72240)
• 12 ns read/write cycle time (IDT72420/72200/72210)
• 15 ns read/write cycle time (IDT72220/72230/72240)
• Read and write clocks can be asynchronous or
coincidental
• Dual-Ported zero fall-through time architecture
• Empty and Full flags signal FIFO status
• Almost-empty and almost-full flags set to Empty+7 and
Full-7, respectively
• Output enable puts output data bus in high-impedance
state
• Produced with advanced submicron CMOS technology
• Available in 28-pin 300 mil plastic DIP and 300 mil
ceramic DIP
• For surface mount product please see the IDT72421/
72201/72211/72221/72231/72241 data sheet
• Military product compliant to MIL-STD-883, Class B
• Industrial temperature range (-40OC to +85OC) is
available, tested to military electrical specifications
DESCRIPTION:
The IDT72420/72200/72210/72220/72230/72240
SyncFIFO™ are very high-speed, low-power First-In, First-
Out (FIFO) memories with clocked read and write controls.
The IDT72420/72200/72210/72220/72230/72240 have a 64,
256, 512, 1024, 2048, and 4096 x 8-bit memory array, respec-
tively. These FIFOs are applicable for a wide variety of data
buffering needs, such as graphics, Local Area Networks
(LANs), and interprocessor communication.
These FIFOs have 8-bit input and output ports. The input
port is controlled by a free-running clock (WCLK), and a write
enable pin (WEN). Data is written into the Synchronous FIFO
on every clock when WEN is asserted. The output port is
controlled by another clock pin (RCLK) and a read enable pin
(REN). The read clock can be tied to the write clock for single
clock operation or the two clocks can run asynchronous of one
another for dual clock operation. An output enable pin (OE) is
provided on the read port for three-state control of the output.
These Synchronous FIFOs have two end-point flags, Empty
(EF) and Full (FF). Two partial flags, Almost-Empty (AE) and
Almost-Full (AF), are provided for improved system control.
The partial ( AE) flags are set to Empty+7 and Full-7 for AE and
AF respectively.
The IDT72420/72200/72210/72220/72230/72240 are fabri-
cated using IDT’s high-speed submicron CMOS technology.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B.
FUNCTIONAL BLOCK DIAGRAM
WCLK
WEN
•
•
WRITE CONTROL
LOGIC
WRITE POINTER
D0 - D7
INPUT REGISTER
••
RAM ARRAY
64 x 8
256 x 8
512 x 8
••
FLAG
LOGIC
READ POINTER
READ CONTROL
LOGIC
EF
AE
AF
FF
OUTPUT REGISTER
•
RESET LOGIC
RS OE
Q0 - Q7
RCLK
REN
The IDT logo is a registered trademark and SyncFIFO is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
5.12
2680 drw 01
NOVEMBER 1996
DSC-2680/6
1

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IDT72220 equivalent
IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO™
64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to + 70°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)
Symbol Parameter
Commercial
72220L12 72220L15
72230L12 72230L15
72240L12 72240L15
Min. Max. Min. Max.
Commercial & Military
72220L20 72220L25
72230L20 72230L25
72240L20 72240L25
Min. Max. Min. Max.
Comm.
72220L35
72230L35
72240L35
Min. Max.
Comm./Mil.
72220L50
72230L50
72240L50
Min. Max.
fS Clock Cycle Frequency
— 83.3 — 66.7 — 50 — 40 — 28.6 — 20
tA Data Access Time
2 8 2 10 2 12 3 15 3 20 3 25
tCLK Clock Cycle Time
12 — 15 — 20 — 25 — 35 — 50 —
tCLKH Clock High Time
5 — 6 — 8 — 10 — 14 — 20 —
tCLKL Clock Low Time
5 — 6 — 8 — 10 — 14 — 20 —
tDS Data Set-up Time
3 — 4 — 5 — 6 — 8 — 10 —
tDH Data Hold Time
.5 — 1 — 1 — 1 — 2 — 2 —
tENS Enable Set-up Time
3 — 4 — 5 — 6 — 8 — 10 —
tENH Enable Hold Time
.5 — 1 — 1 — 1 — 2 — 2 —
tRS Reset Pulse Width(1)
12 — 15 — 20 — 25 — 35 — 50 —
tRSS Reset Set-up Time
12 — 15 — 20 — 25 — 35 — 50 —
tRSR Reset Recovery Time
12 — 15 — 20 — 25 — 35 — 50 —
tRSF Reset to Flag and Output Time
— 12 — 15 — 20 — 25 — 35 — 50
tOLZ Output Enable to Output in Low-Z(2) 0 — 0 — 0 — 0 — 0 — 0 —
tOE Output Enable to Output Valid
3 7 3 8 3 10 3 13 3 15 3 23
tOHZ Output Enable to Output in High-Z(2) 3 7 3 8 3 10 3 13 3 15 3 23
tWFF Write Clock to Full Flag
— 8 — 10 — 12 — 15 — 20 — 30
tREF Read Clock to Empty Flag
— 8 — 10 — 12 — 15 — 20 — 30
tAF Write Clock to Almost-Full Flag
— 8 — 10 — 12 — 15 — 20 — 30
tAE Read Clock to Almost-Empty Flag
— 8 — 10 — 12 — 15 — 20 — 30
tSKEW1 Skew time between Read Clock
& Write Clock for Empty Flag &
Full Flag
tSKEW2 Skew time between Read Clock &
Write Clock for Almost-Empty Flag
& Almost-Full Flag
5 — 6 — 8 — 10 — 12 — 15 —
22 — 28 — 35 — 40 — 42 — 45 —
NOTES:
1. Pulse widths less than minimum values are not allowed.
2. Values guaranteed by design, not currently tested.
5V
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2680 tbl 08
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Figure 1
2680 tbl 09
D.U.T.
680Ω
1.1KΩ
30pF*
2680 drw 03
or equivalent circuit
Figure 1. Output Load
*Includes jig and scope capacitances.
5.12 5


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Part Details

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