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PDF IDT7210 Data sheet ( Hoja de datos )
| Número de pieza | IDT7210 | |
| Descripción | 16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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16 x 16 PARALLEL CMOS
MULTIPLIER-ACCUMULATOR
IDT7210L
Integrated Device Technology, Inc.
FEATURES:
• 16 x 16 parallel multiplier-accumulator with selectable
accumulation and subtraction
• High-speed: 20ns multiply-accumulate time
• IDT7210 features selectable accumulation, subtraction,
rounding and preloading with 35-bit result
• IDT7210 is pin and function compatible with the TRW
TDC1010J, TMC2210, Cypress CY7C510, and AMD
AM29510
• Performs subtraction and double precision addition and
multiplication
• Produced using advanced CMOS high-performance
technology
• TTL-compatible
• Available in topbraze DIP, PLCC, Flatpack and Pin Grid
Array
• Military product compliant to MIL-STD-883, Class B
• Standard Military Drawing #5962-88733 is listed on this
function
• Speeds available:
Commercial: L20/25/35/45/55/65
Military: L25/30/40/55/65/75
DESCRIPTION:
The IDT7210 is a high-speed, low-power 16 x 16-bit parallel
multiplier-accumulator that is ideally suited for real-time digital
signal processing applications. Fabricated using CMOS
silicon gate technology, this device offers a very low-power
alternative to existing bipolar and NMOS counterparts, with
only 1/7 to 1/10 the power dissipation and exceptional speed
(25ns maximum) performance.
A pin and functional replacement for TRW’s TDC1010J the
IDT7210 operates from a single 5 volt supply and is compatible
with standard TTL logic levels. The architecture of the IDT7210
is fairly straightforward, featuring individual input and output
registers with clocked D-type flip-flop, a preload capability
which enables input data to be preloaded into the output
registers, individual three-state output ports for the Extended
Product (XTP) and Most Significant Product (MSP) and a
Least Significant Product output (LSP) which is multiplexed
with the Y input.
The XIN and YIN data input registers may be specified
through the use of the Two’s Complement input (TC) as either
a two’s complement or an unsigned magnitude, yielding a full-
precision 32-bit result that may be accumulated to a full 35-bit
result. The three output registers – Extended Product (XTP),
Most Most Significant Product (MSP) and Least Significant
Product (LSP) – are controlled by the respective TSX, TSM
and TSL input lines. The LSP output can be routed through YIN
ports.
FUNCTIONAL BLOCK DIAGRAM
CLKX
XIN
(X15-X0)
16
ACC, SUB,
RND, TC
4
YIN
CLKY (Y15-Y0/P15-P0)
16
XREGISTER
CONTROL
REGISTER
YREGISTER
MULTIPLIER ARRAY
32 +
TSL
+/–
ACCUMULATOR
PREL
35
CLKP
TSX
35
XTP REGISTER MSP REGISTER LSP REGISTER
3
TSM
16
3
XTPOUT
(P34-P32)
PREL
16
MSPOUT
(P31-P16)
IDT7210
2577 drw 01
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1995 Integrated Device Technology, Inc.
11.2
AUGUST 1995
DSC-2018/7
1
1 page  
IDT7210L
16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)
Symbol
Parameter
VIH Input High Voltage
Test Conditions(5)
Guaranteed Logic HIGH Level
Commercial
Min. Typ.(1) Max.
2.0 — —
Military
Min. Typ.(1) Max.
2.0 — —
Unit
V
VIL Input Low Voltage
Guaranteed Logic LOW Level —
— 0.8 —
— 0.8
V
|ILI| Input Leakage Current
VCC = Max., VIN = 0V to VCC
—
—
10
—
—
10 µA
|ILO| Output Leakage Current
VOH Output HIGH Voltage
VCC = Max., Outputs Disabled — — 10 — — 10 µA
VOUT = 0 to VCC
VCC = Min., IOH = –2.0mA
2.4 — — 2.4 — —
V
VOL(4) Output LOW Voltage
VCC = Min., IOL = 4mA
— — 0.4 — — 0.4 V
IOS Output Short Circuit Current
VCC = Max., V0 GND
-20 — -100 -20 — -100 mA
ICC(2) Operating Power Supply Current VCC = Max., Outputs Enabled — 45 90 — 45 110 mA
f= 10MHz(2)
CL = 50 pF
ICCQ1 Quiescent Power Supply Current VIN ≥ VIH, VIN ≤ VIL
— 20 30 — 20 30 mA
ICCQ2 Quiescent Power Supply Current VIN ≥ VCC –0.2V, V IN ≤ 0.2V — 4 10 — 4 12 mA
ICC/f(2,3) Increase in Power Supply
VCC = Max., Outputs Disabled —
—
6
——
8 mA/
Current MHz
MHz
NOTES:
2577 tbl 05
1. Typical implies VCC = 5V and TA = +25°C.
2. ICC is measured at 10MHz and VIN = 0 to 3V. For frequencies greater than 10MHz, the following equation is used for the commercial range:
ICC = 90+ 6(f –10)mA, where f = operating frequency in MHz. For the military range, ICC = 110 + 8(f –10). f = operating frequency in MHz, f = 1/tMA.
3. For frequencies greater than 10MHz, guaranteed by design, not production tested.
4. IOL = 4mA for tMA > 55ns.
5. For conditions shown as Max. or Min., use appropriate value specified under electrical characteristics.
AC ELECTRICAL CHARACTERISTICS COMMERCIAL (VCC = 5V ± 10%, TA = 0° to +70°C)
7210L20 7210L25 7210L35 7210L45 7210L55 7210L65
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tMA Multiply-Accumulate Time(2)
2.0 20 2.0 25 2.0 35 2.0 45 2.0 55 2.0 65 ns
tD Output Delay(2)
2.0 18 2.0 20 2.0 25 2.0 25 2.0 30 2.0 35 ns
tENA
3-State Enable Time
— 18 – 20 – 25 – 25 – 30 – 30 ns
tDIS 3-State Disable Time(1)
— 18 – 20 – 25 – 25 – 30 – 30 ns
tS Input Register Set-up Time
10 — 12 – 12 – 15 – 20 – 25 – ns
tH Input Register Hold Time
3 — 3 – 3 – 3 – 3 – 3 – ns
tPW Clock Pulse Width
9 — 10 – 10 – 15 – 20 – 25 – ns
tHCL
Relative Hold Time
0 — 0 – 0 – 0 – 0 – 0 – ns
NOTES:
1. Transition is measured ±500mV from steady state voltage.
2. Minimum delays guaranteed but not tested
2577 tbl 06
AC ELECTRICAL CHARACTERISTICS MILITARY (VCC = 5V ± 10%, TA = –55° to +125°C)
7210L25 7210L30 7210L40 7210L55 7210L65 7210L75
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tMA
tD
tENA
tDIS
tS
tH
tPW
tHCL
Multiply-Accumulate Time(2)
Output Delay(2)
3-State Enable Time
3-State Disable Time(1)
Input Register Set-up Time
Input Register Hold Time
Clock Pulse Width
Relative Hold Time
2.0 25 2.0 30 2.0 40 2.0 55 2.0 65 2.0 75
2.0 20 2.0 20 2.0 25 2.0 30 2.0 35 2.0 35
— 20 – 20 – 25 – 30 – 30 – 35
— 20 – 20 – 25 – 25 – 30 – 30
12 — 12 – 15 – 20 – 25 – 25 –
3—3 – 3 – 3 – 3 – 3 –
10 — 10 – 15 – 20 – 25 – 25 –
0—0 – 0 – 0 – 0 – 0 –
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. Transition is measured ±500mV from steady state voltage.
2. Minimum delays guaranteed but not tested
2577 tbl 07
11.2 5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet IDT7210.PDF ] | |
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