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PDF 6259 Data sheet ( Hoja de datos )
| Número de pieza | 6259 | |
| Descripción | 8-BIT ADDRESSABLE DMOS POWER DRIVER | |
| Fabricantes | Allegro MicroSystems | |
| Logotipo |  |
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6259
ADVANCE INFORMATION
(Subject to change without notice)
January 24, 2000
POWER
GROUND
1
LOGIC
SUPPLY
2
VDD
S 0 (LSB) 3
OUT 0 4
OUT1 5
OUT 2 6
OUT 3 7
S1 8
LOGIC 9
GROUND
POWER 10
GROUND
20
POWER
GROUND
19 CLEAR
18 DATA
17 OUT7
16 OUT6
15 OUT5
14 OUT 4
EN 13 ENABLE
12 S2 (MSB)
11 POWER
GROUND
Dwg. PP-050-2
Note that the A6259KA (DIP) and the A6259KLW
(SOIC) are electrically identical and share a
common terminal number assignment.
ABSOLUTE MAXIMUM RATINGS
at TA = 25°C
Output Voltage, VO ............................ 50 V
Output Drain Current,
Continuous, IO ...................... 250 mA*
Peak, IOM ............................. 750 mA*†
Peak, IOM ................................... 2.0 A†
Single-Pulse Avalanche Energy,
EAS ............................................. 75 mJ
Logic Supply Voltage, VDD .............. 7.0 V
Input Voltage Range,
VI ............................... -0.3 V to +7.0 V
Package Power Dissipation,
PD ....................................... See Graph
Operating Temperature Range,
TA ............................. -40°C to +125°C
Storage Temperature Range,
TS ............................. -55°C to +150°C
*Each output, all outputs on.
† Pulse duration ≤ 100 µs, duty cycle ≤ 2%.
Caution: These CMOS devices have input static
protection (Class 3) but are still susceptible to
damage if exposed to extremely high static
electrical charges.
8-BIT ADDRESSABLE
DMOS POWER DRIVER
The A6259KA and A6259KLW combine a 3-to-8 line CMOS
decoder and accompanying data latches, control circuitry, and DMOS
outputs in a multi-functional power driver capable of storing single-line
data in the addressable latches or use as a decoder or demuliplexer.
Driver applications include relays, solenoids, and other medium-current
or high-voltage peripheral power loads.
The CMOS inputs and latches allow direct interfacing with micro-
processor-based systems. Use with TTL may require appropriate pull-
up resistors to ensure an input logic high. Four modes of operation are
selectable with the CLEAR and ENABLE inputs.
The addressed DMOS output inverts the DATA input with all
unaddressed outputs remaining in their previous states. All of the output
drivers are disabled (the DMOS sink drivers turned off) with the
CLEAR input low and the ENABLE input high. The A6259KA/KLW
DMOS open-drain outputs are capable of sinking up to 750 mA. Similar
devices with reduced rDS(on) are available as the A6A259.
The A6259KA is furnished in a 20-pin dual in-line plastic package.
The A6259KLW is furnished in a 20-lead wide-body, small-outline
plastic package (SOIC) with gull-wing leads for surface-mount applica-
tions. Copper lead frames, reduced supply current requirements, and
low on-state resistance allow both devices to sink 150 mA from all
outputs continuously, to ambient temperatures over 85°C.
FEATURES
s 50 V Minimum Output Clamp Voltage
s 250 mA Output Current (all outputs simultaneously)
s 1.3 Ω Typical rDS(on)
s Low Power Consumption
s Replacements for TPIC6259N and TPIC6259DW
Always order by complete part number:
Part Number
A6259KA
A6259KLW
Package
20-pin DIP
20-lead SOIC
RθJA
55°C/W
70°C/W
RθJC
25°C/W
17°C/W
1 page  
6259
8-BIT ADDRESSABLE
DMOS POWER DRIVER
FUNCTIONAL DESCRIPTION and INPUT REQUIREMENTS
ENABLE
DATA
ADDRESSED
OUTPUT
50%
t PLH
10%
tr
t PHL
90%
tf
OUTPUT SWITCHING TIME
Dwg. WP-036
ENABLE
DATA
50%
t su(D)
t h(D)
50%
t w(D)
Dwg. WP-037
DATA INPUT REQUIREMENTS
Data Active Time Before Enable
(Data Set-Up Time), tsu(D) .............................................. 20 ns
Data Active Time After Enable
(Data Hold Time), th(D) ................................................... 20 ns
Data Pulse Width, tw(D) ....................................................... 40 ns
Input Logic High, VIH ................................................ ≥ 0.85VDD
Input Logic Low, VIL ................................................. ≤ 0.15VDD
Four modes of operation are selectable by controlling
the CLEAR and ENABLE inputs as shown above.
In the addressable-latch mode, data at the DATA input
is written into the addressed transparent latch. The
addressed output inverts the data input with all other
outputs remaining in their previous states.
In the memory mode, all outputs remain in their
previous states and are unaffected by the DATA or
address (Sn) inputs. To prevent entering erroneus data in
the latches, ENABLE should be held HIGH while the
address lines are changing.
In the demultiplexing/decoding mode, the addressed
output inverts the data input and all other outputs are OFF.
In the clear mode, all outputs are OFF and are unaf-
fected by the DATA or address (SN) inputs.
Given the appropriate inputs, when DATA is LOW
for a given address, the output is OFF; when DATA is
HIGH, the output is ON and can sink current.
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