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PDF 61SP6464 Data sheet ( Hoja de datos )
| Número de pieza | 61SP6464 | |
| Descripción | 64K x 64 SYNCHRONOUS PIPELINE STATIC RAM | |
| Fabricantes | Integrated Silicon Solution Inc | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de 61SP6464 (archivo pdf) en la parte inferior de esta página. Total 19 Páginas | ||
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IS61SP6464
64K x 64 SYNCHRONOUS
PIPELINE STATIC RAM
ISSI ®
JANUARY 2004
FEATURES
• Fast access time:
– 117, 100 MHz
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Pentium™ or linear burst sequence control
using MODE input
• Five chip enables for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• Power-down control by ZZ input
• JEDEC 128-Pin TQFP 14mm x 20mm
package
• Single +3.3V power supply
• Control pins mode upon power-up:
– MODE in interleave burst mode
– ZZ in normal operation mode
These control pins can be connected to GNDQ
or VDDQ to alter their power-up state
DESCRIPTION
The ISSI IS61SP6464 is a high-speed, low-power synchronous
static RAM designed to provide a burstable, high-performance,
secondary cache for the i486™, Pentium™, 680X0™, and
PowerPC™ microprocessors. It is organized as 65,536 words
by 64 bits, fabricated with ISSI's advanced CMOS technology.
The device integrates a 2-bit burst counter, high-speed SRAM
core, and high-drive capability outputs into a single monolithic
circuit. All synchronous inputs pass through registers con-
trolled by a positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one to
eight bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written. BW1
controls I/O1-I/O8, BW2 controls I/O9-I/O16, BW3 controls I/
O17-I/O24, BW4 controls I/O25-I/O32, BW5 controls
I/O33-I/O40, BW6 controls I/O41-I/O48, BW7 controls I/O49-I/
O56, BW8 controls I/O57-I/O64, conditioned by BWE being
LOW. A LOW on GW input would cause all bytes to be written.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller) input
pins. Subsequent burst addresses can be generated internally
by the IS61SP6464 and controlled by the ADV (burst address
advance) input pin.
Asynchronous signals include output enable (OE), sleep mode
input (ZZ), and burst mode input (MODE). A HIGH input on the
ZZ pin puts the SRAM in the power-down state. When ZZ is
pulled LOW (or no connect), the SRAM normally operates after
the wake-up period. A LOW input, i.e., GNDQ, on MODE pin
selects LINEAR Burst. A VDDQ (or no connect) on MODE pin
selects INTERLEAVED Burst.
Copyright © 2004 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
01/14/04
1
1 page  
IS61SP6464
ASYNCHRONOUS TRUTH TABLE
Operation
ZZ
Pipelined Read
Pipelined Read
Write
Write
L
L
L
L
Deselect
L
Sleep
H
OE
L
H
L
H
X
X
I/O STATUS
Dout
High-Z
High-Z
Din
High-Z
High-Z
ISSI®
WRITE TRUTH TABLE
Operation
GW
Read
Read
Write all bytes
Write all bytes
Write Byte 1
Write Byte 2
Write Byte 3
Write Byte 4
Write Byte 5
Write Byte 6
Write Byte 7
Write Byte 8
H
H
H
L
H
H
H
H
H
H
H
H
BWE
H
L
L
X
L
L
L
L
L
L
L
L
BW8
X
H
L
X
H
H
H
H
H
H
H
L
BW7
X
H
L
X
H
H
H
H
H
H
L
H
BW6
X
H
L
X
H
H
H
H
H
L
H
H
BW5
X
H
L
X
H
H
H
H
L
H
H
H
BW4
X
H
L
X
H
H
H
L
H
H
H
H
BW3
X
H
L
X
H
H
L
H
H
H
H
H
BW2
X
H
L
X
H
L
H
H
H
H
H
H
BW1
X
H
L
X
L
H
H
H
H
H
H
H
INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or No Connect)
External Address
A1 A0
1st Burst Address
A1 A0
2nd Burst Address
A1 A0
3rd Burst Address
A1 A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
01/14/04
5
5 Page 
IS61SP6464
WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
Symbol
tKC
tKH
tKL
tAS
tSS
tWS
tDS
tCES
tAVS
tAH
tSH
tDH
tWH
tCEH
tAVH
Parameter
Cycle Time
Clock High Time
Clock Low Time
Address Setup Time
Address Status Setup Time
Write Setup Time
Data In Setup Time
Chip Enable Setup Time
Address Advance Setup Time
Address Hold Time
Address Status Hold Time
Data In Hold Time
Write Hold Time
Chip Enable Hold Time
Address Advance Hold Time
-117MHz
Min. Max.
9.2 —
3.4 —
3.4 —
2.5 —
2.5 —
2.5 —
2.5 —
2.5 —
2.5 —
0.5 —
0.5 —
0.5 —
0.5 —
0.5 —
0.5 —
-100 MHz
Min. Max.
10 —
4—
4—
2.5 —
2.5 —
2.5 —
2.5 —
2.5 —
2.5 —
0.5 —
0.5 —
0.5 —
0.5 —
0.5 —
0.5 —
ISSI®
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. C
01/14/04
11
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet 61SP6464.PDF ] | |
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