PDF 74AC399SC Data sheet ( Hoja de datos )

Número de pieza	74AC399SC
Descripción	Quad 2-Port Register
Fabricantes	Fairchild Semiconductor
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No Preview Available ! June 1988 Revised October 2000 74AC399 • 74ACT399 Quad 2-Port Register General Description The AC/ACT399 is the logical equivalent of a quad 2-input multiplexer feeding into four edge-triggered flip-flops. A common Select input determines which of the two 4-bit words is accepted. The selected data enters the flip-flop on the rising edge of the clock. Features s ICC reduced by 50% s Select inputs from two data sources s Fully positive edge-triggered operation s Outputs source/sink 24 mA s AC/ACT399 has TTL-compatible inputs Ordering Code: Order Number Package Number Package Description 74AC399SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74AC399PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 74ACT399SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74ACT399SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACT399MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74ACT399PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols www.DataSheet4U.com Connection Diagram IEEE/IEC Pin Descriptions Pin Names S CP I0a–I0d I1a–I1d Qa–Qd Description Common Select Input Clock Pulse Input Data Inputs from Source 0 Data Inputs from Source 1 Register True Outputs FACT is a trademark of Fairchild Semiconductor Corporation. © 2000 Fairchild Semiconductor Corporation DS009789 www.fairchildsemi.com 1 page AC Operating Requirements for AC Symbol Parameter tS Setup Time, HIGH or LOW In to CP tH Hold Time, HIGH or LOW In to CP tS Setup Time, HIGH or LOW S to CP tH Hold Time, HIGH or LOW S to CP tW CP Pulse Width, HIGH or LOW Note 8: Voltage Range 5.0 is 5.0V ± 0.5V VCC (V) (Note 8) 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 TA = +25°C TA = −40°C to +85°C CL = 50 pF CL = 50 pF Typ Guaranteed Minimum 2.0 4.0 4.0 1.5 3.0 3.0 0.5 1.0 1.0 0.5 1.0 1.0 3.5 5.5 5.5 2.0 4.0 4.0 0.5 1.0 1.0 0.5 1.0 1.0 3.0 4.5 4.5 2.0 3.5 3.5 Units ns ns ns ns ns AC Electrical Characteristics for ACT Symbol Parameter fMAX tPLH Input Clock Frequency Propagation Delay CP to Q tPHL Propagation Delay CP to Q Note 9: Voltage Range 5.0 is 5.0V ± 0.5V VCC (V) (Note 9) 5.0 5.0 5.0 TA = +25°C VCC = +5.0V CL = 50 pF Min Typ Max 165 180 1.5 7.0 8.0 2.0 6.0 9.0 TA = −40°C to +85°C VCC = 5.0V CL = 50pF Min Max 160 1.5 8.5 2.0 9.5 Units MHz ns ns AC Operating Requirements for ACT Symbol Parameter tS Setup Time, HIGH or LOW In to CP tH Hold Time, HIGH or LOW In to CP tS Setup Time, HIGH or LOW S to CP tH Hold Time, HIGH or LOW S to CP tW CP Pulse Width, HIGH or LOW Note 10: Voltage Range 5.0 is 5.0V ± 0.5V VCC (V) (Note 10) 5.0 5.0 5.0 5.0 5.0 TA = +25°C TA = −40°C to +85°C CL = 50 pF CL = 50 pF Typ Guaranteed Minimum 0.8 2.5 2.5 0 1.0 1.0 0.8 4.0 4.0 −1.0 0.5 0.5 1.7 3.5 3.5 Units ns ns ns ns ns Capacitance Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Typ Units Conditions 4.5 pF VCC = OPEN 30 pF VCC = 5.0V 5 www.fairchildsemi.com 5 Page

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