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PDF 74AC374 Data sheet ( Hoja de datos )
| Número de pieza | 74AC374 | |
| Descripción | OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT NON INVERTING | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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74AC374
OCTAL D-TYPE FLIP FLOP
WITH 3 STATE OUTPUT NON INVERTING
s HIGH SPEED:
s fMAX = 270 MHz (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 8 µA (MAX.) at TA = 25 oC
s HIGH NOISE IMMUNITY:
VNIH = VNIL = 28% VCC (MIN.)
s 50Ω TRANSMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24 mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 6V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 374
s IMPROVED LATCH-UP IMMUNITY
BM
(Plastic Package)
(Micro Package)
ORDER CODES :
74AC374B
74AC374M
clock input (CK) and an output enable input (OE).
On the positive transition of the clock, the Q
outputs will be set to the logic state that were
setup at the D inputs.
While the (OE) input is low, the 8 outputs will be
in a normal logic state (high or low logic level)
and while high level the outputs will be in a high
DESCRIPTION
impedance state.
The AC374 is an advanced high-speed CMOS Thewww.DataSheet4U.com output control does not affect the internal
OCTAL D-TYPE FLIP FLOP with 3 STATE
OUTPUT NON INVERTING fabricated with
sub-micron silicon gate and double-layer metal
operation of flip flops; that is, the old data can be
retained or the new data can be entered even
while the outputs are off.
wiring C2MOS technology. It is ideal for low All inputs and outputs are equipped with
power applications mantaining high speed protection circuits against static discharge, giving
operation similar to equivalent Bipolar Schottky them 2KV ESD immunity and transient excess
TTL.
voltage.
These 8 bit D-Type flip-flops are controlled by a
PIN CONNECTION AND IEC LOGIC SYMBOLS
April 1997
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1 page  
74AC374
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf =3 ns)
Symbol
P ar ame te r
tPLH Propagation Delay Time
tPHL CK to Q
tPZL Output EnableTime
tPZH
tPLZ Output Disable Time
tPHZ
tw Clock Pulse Width HIGH
or LOW
ts Setup Time Q to CK
HIGH or LOW
th Hold Time Q to CK
HIGH or LOW
fMAX Maximum Clock
Frequency
(*) Voltage range is 3.3V ± 0.3V
(**) Voltage range is 5V ± 0.5V
Test Condition
V CC
(V)
3.3(*)
5.0(**)
3.3(*)
5.0(**)
3.3(*)
5.0(**)
3.3(*)
5.0(**)
3.3(*)
5.0(**)
3.3(*)
5.0(**)
3.3(*)
5.0(**)
Value
TA = 25 oC
-40 to 85 oC
Min. Typ. Max. Min. Max.
6.5 12
13
59
10
7.5 12
13
5.5 9
10
7.5 12
13
69
10
1.5 5
6
1.5 4
5
-0.5 5
5
-0.5 4
4
0.5 2
3
0.5 2
3
60 250
60
100 270
100
Unit
ns
ns
ns
ns
ns
ns
MHz
CAPACITIVE CHARACTERISTICS
Symbol
P ar ame te r
Test Conditions
V CC
(V)
Value
TA = 25 oC
-40 to 85 oC
Min. Typ. Max. Min. Max.
Unit
COUT Output Capacitance
5.0
8 pF
CIN Input Capacitance
5.0
4 pF
CPD Power Dissipation
Capacitance (note 1)
5.0
46 pF
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to
Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD • VCC • fIN + ICC/n (per circuit)
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| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet 74AC374.PDF ] | |
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