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PDF 74AC163B Data sheet ( Hoja de datos )
| Número de pieza | 74AC163B | |
| Descripción | SYNCHRONOUS PRESETTABLE 4-BIT COUNTER | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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54AC16374, 74AC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS123B – MARCH 1990 – REVISED APRIL 1996
D Members of the Texas Instruments
Widebus ™ Family
D 3-State True Outputs
D Full Parallel Access for Loading
D Flow-Through Architecture Optimizes
PCB Layout
D Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D EPIC™ (Enhanced-Performance Implanted
CMOS) 1-µm Process
D 500-mA Typical Latch-Up Immunity at
125°C
D Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Packages Using
25-mil Center-to-Center Pin Spacings and
380-mil Fine-Pitch Ceramic Flat (WD)
Packages Using 25-mil Center-to-Center
Pin Spacings
description
The ’AC16374 are 16-bit edge-triggered D-type
flip-flops with 3-state outputs designed
specifically for driving highly capacitive or
relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
54AC16374 . . . WD PACKAGE
74AC16374 . . . DL PACKAGE
(TOP VIEW)
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 1CLK
47 1D1
46 1D2
45 GND
44 1D3
43 1D4
42 VCC
41 1D5
40 1D6
39 GND
38 1D7
37 1D8
36 2D1
35 2D2
34 GND
33 2D3
32 2D4
31 VCC
30 2D5
29 2D6
28 GND
27 2D7
26 2D8
25 2CLK
The ’AC16374 can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock
(CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly.
OE does not affect the internal operations of the flip-flop. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The 74AC16374 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and
functionality of standard small-outline packages in the same printed-circuit-board area.
The 54AC16374 is characterized for operation over the full military temperature range of –55°C to 125°C. The
74AC16374 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
•POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1996, Texas Instruments Incorporated
1
1 page  
54AC16374, 74AC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS123B – MARCH 1990 – REVISED APRIL 1996
timing requirements over recommended operating free-air temperature range
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
TA = 25°C
54AC16374
MIN MAX MIN MAX
fclock
tw
tsu
th
Clock frequency
Pulse duration
Setup time, data before CLK↑
Hold time, data after CLK↑
CLK high or low
0 60
0 60
8.3 8.3
7.5 7.5
00
74AC16374
MIN MAX
0 60
8.3
7.5
0
UNIT
MHz
ns
ns
ns
timing requirements over recommended operating free-air temperature range
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
TA = 25°C
54AC16374
MIN MAX MIN MAX
fclock
tw
tsu
th
Clock frequency
Pulse duration
Setup time, data before CLK↑
Hold time, data after CLK↑
CLK high or low
0 100
5
5
0
0 100
5
5
0
74AC16374
MIN MAX
0 100
5
5
0
UNIT
MHz
ns
ns
ns
switching characteristics over recommended operating free-air temperature range
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TA = 25°C
54AC16374 74AC16374
MIN TYP MAX MIN MAX MIN MAX
fmax
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
CLK
OE
OE
60 60 60
4.9 12.2
15 4.9
17 4.9
17
Q
4.8 11.9 14.3 4.8 15.7 4.8 15.7
4.3 11.9 14.7 4.3 16.8 4.3 16.8
Q
5.3 15.5 18.7 5.3 21.2 5.3 21.2
4 7.3 9 4 9.8 4 9.8
Q
3.8 7.1 8.8 3.8 9.4 3.8 9.4
UNIT
MHz
ns
ns
ns
switching characteristics over recommended operating free-air temperature range
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TA = 25°C
54AC16374 74AC16374
MIN TYP MAX MIN MAX MIN MAX
fmax
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
CLK
OE
OE
100 100 100
3.8 7.6 9.5 3.8 10.8 3.8 10.8
Q
3.8 7.6 9.5 3.8 10.6 3.8 10.6
3.2 7.2
9 3.2 10.2 3.2 10.2
Q
3.8 8.7 10.7 3.8 12.1 3.8 12.1
3.7 6 7.5 3.7 8.2 3.7 8.2
Q
3.5 5.8 7.3 3.5 7.9 3.5 7.9
UNIT
MHz
ns
ns
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd Power dissipation capacitance per flip-flop
Outputs enabled
Outputs disabled
TEST CONDITIONS
CL = 50 pF, f = 1 MHz
TYP UNIT
49
pF
32
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
•POST OFFICE BOX 655303 DALLAS, TEXAS 75265
5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet 74AC163B.PDF ] | |
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