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74AC138B fiches techniques PDF

STMicroelectronics - 3 TO 8 LINE DECODER INVERTING

Numéro de référence 74AC138B
Description 3 TO 8 LINE DECODER INVERTING
Fabricant STMicroelectronics 
Logo STMicroelectronics 





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74AC138B fiche technique
74AC138
3 TO 8 LINE DECODER (INVERTING)
s HIGH SPEED: tPD = 4.5ns (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 4µA(MAX.) at TA=25°C
s HIGH NOISE IMMUNITY:
VNIH = VNIL = 28 % VCC (MIN.)
s 50TRANSMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 6V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 138
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74AC138 is an advanced high-speed CMOS
3 TO 8 LINE DECODER (INVERTING) fabricated
with sub-micron silicon gate and double-layer
metal wiring C2MOS tecnology.
If the device is enabled, 3 binary select inputs (A,
B, and C) determine which one of the outputs will
go low. If enable input G1 is held low or either G2A
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
DIP
SOP
TSSOP
TUBE
74AC138B
74AC138M
T&R
74AC138MTR
74AC138TTR
or G2B is held high, the decoding function is
inhibited and all the 8 outputs go to high.
Tree enable inputs are provided to ease cascade
connection and application of address decoders
for memory systems.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
April 2001
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