(PDF) 74AC125 Datasheet - QUAD BUS BUFFERS 3-STATE

Número de pieza	74AC125
Descripción	QUAD BUS BUFFERS 3-STATE
Fabricantes	STMicroelectronics
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No Preview Available ! 74AC125 QUAD BUS BUFFERS (3-STATE) s HIGH SPEED: tPD = 4ns (TYP.) at VCC = 5V s LOW POWER DISSIPATION: ICC = 4µA(MAX.) at TA=25°C s HIGH NOISE IMMUNITY: VNIH = VNIL = 28 % VCC (MIN.) s 50Ω TRANSMISSION LINE DRIVING CAPABILITY s SYMMETRICAL OUTPUT IMPEDANCE: \|IOH\| = IOL = 24mA (MIN) s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL s OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V s PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 125 s IMPROVED LATCH-UP IMMUNITY DESCRIPTION The 74AC125 is an advanced high-speed CMOS QUAD BUS BUFFER fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. DIP SOP TSSOP ORDER CODES PACKAGE DIP SOP TSSOP TUBE 74AC125B 74AC125M T&R 74AC125MTR 74AC125TTR The device requires the 3-STATE control input G to be set high to place the output go in to the high impedance state. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS July 2001 1/9 1 page WAVEFORM 1: PROPAGATION DELAYS (f=1MHz; 50% duty cycle) 74AC125 WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle) 5/9 5 Page

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PDF 74AC125 Data sheet ( Hoja de datos )