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PDF 74ABT845N Data sheet ( Hoja de datos )
| Número de pieza | 74ABT845N | |
| Descripción | 8-bit bus interface latch with set and reset 3-State | |
| Fabricantes | NXP Semiconductors | |
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Philips Semiconductors
8-bit bus interface latch with set and reset
(3-State)
Product specification
74ABT845
FEATURES
• High speed parallel latches
• Ideal where high speed, light loading, or increased fan-in are
required with MOS microprocessors
• Broadside pinout
• Output capability: +64mA/–32mA
• Power-up 3-State
• Power-up reset
• Latch-up protection exceeds 500mA per Jedec Std 17
• ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
DESCRIPTION
The 74ABT845 consists of eight D-type latches with 3-State outputs.
In addition to the LE, OE, MR and PRE pins, the 74ABT845 has two
additional OE pins, making a total of three Output Enable (OE0,
OE1, OE2) pins. The multiple Output enables allow multiuser control
of the interface, e.g., CS, DMA, and RD/WR.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
tPLH
tPHL
CIN
COUT
ICCZ
Propagation delay
Dn to Qn
Input capacitance
Output capacitance
Total supply current
CONDITIONS
Tamb = 25°C; GND = 0V
CL = 50pF; VCC = 5V
VI = 0V or VCC
Outputs disabled;
VO = 0V or VCC
Outputs disabled; VCC = 5.5V
TYPICAL
5.4
4
7
500
UNIT
ns
pF
pF
nA
ORDERING INFORMATION
PACKAGES
24-Pin Plastic DIP
24-Pin plastic SO
24-Pin Plastic SSOP Type II
24-Pin Plastic TSSOP Type I
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
–40°C to +85°C
74ABT845 N
–40°C to +85°C
74ABT845 D
–40°C to +85°C
74ABT845 DB
–40°C to +85°C
74ABT845 PW
NORTH AMERICA
74ABT845 N
74ABT845 D
74ABT845 DB
74ABT845PW DH
DWG NUMBER
SOT222-1
SOT137-1
SOT340-1
SOT355-1
PIN CONFIGURATION
OE0 1
OE1 2
D0 3
D1 4
D2 5
D3 6
D4 7
D5 8
D6 9
D7 10
MR 11
GND 12
24 VCC
23 OE2
22 Q0
21 Q1
20 Q2
19 Q3
18 Q4
17 Q5
16 Q6
15 Q7
14 PRE
13 LE
TOP VIEW
PIN DESCRIPTION
PIN NUMBER SYMBOL
FUNCTION
1, 2, 23
OE0 – OE2
Output enable inputs
(active-Low)
3, 4, 5, 6,
7, 8, 9, 10
D0-D7 Data inputs
22, 21, 20, 19,18,
17, 16, 15
Q0-Q7
Data outputs
11 MR Master reset input (active-Low)
13
LE
Latch enable input
(active-High)
14
PRE
Preset input (active-Low)
12 GND Ground (0V)
24 VCC Positive supply voltage
SA00258
1995 Sep 06
1 853-1703 15702
1 page  
Philips Semiconductors
8-bit bus interface latch with set and reset
(3-State)
Product specification
74ABT845
AC CHARACTERISTICS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω
SYMBOL
PARAMETER
WAVEFORM
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
Propagation delay
Dn to Qn
Propagation delay
LE to Qn
Propagation delay
PRE to Qn
Propagation delay
MR to Qn
Output enable time
OEn to Qn
Output disable time
OEn to Qn
1
2
1
1
4
5
4
5
LIMITS
Tamb = +25oC
VCC = +5.0V
Min Typ Max
1.0 3.9 5.4
2.2 5.4 6.8
2.0 5.1 6.6
2.8 6.4 7.9
2.2 4.9 6.6
3.0 5.3 6.8
2.4 4.9 6.4
3.1 5.9 7.3
1.0 3.8 5.4
2.0 4.7 6.1
1.9 4.6 6.2
2.2 4.7 6.4
Tamb = -40 to
+85oC
VCC = +5.0V ±0.5V
Min Max
1.0 6.2
2.2 7.8
2.0 7.5
2.8 8.9
2.2 7.8
3.0 7.4
2.4 7.3
3.1 8.5
1.0 6.3
2.0 6.7
1.9 7.2
2.2 7.0
UNIT
ns
ns
ns
ns
ns
ns
AC SETUP REQUIREMENTS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω
SYMBOL
PARAMETER
ts(H)
ts(L)
th(H)
th(L)
tw(H)
tw(L)
tw(L)
trec
trec
Setup time, High or Low
Dn to LE
Hold time, High or Low
Dn to LE
LE pulse width, High
PRE pulse width, Low
MR pulse width, Low
PRE recovery time
MR recovery time
WAVEFORM
3
3
3
6
6
6
6
LIMITS
Tamb = +25oC
VCC = +5.0V
Min Typ
Tamb = -40 to +85oC
VCC = +5.0V ±0.5V
Min
2.8 1.0
3.5 1.4
2.8
3.5
1.0 –1.2
1.0 –0.6
1.0
1.0
3.0 1.5
3.0
3.5 2.0
3.5
2.8 1.3
2.8
3.0 1.4
3.0
3.4 1.6
3.4
UNIT
ns
ns
ns
ns
ns
ns
ns
1995 Sep 06
5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet 74ABT845N.PDF ] | |
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