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PDF 74ABT544 Data sheet ( Hoja de datos )
| Número de pieza | 74ABT544 | |
| Descripción | Octal latched transceiver with dual enable/ inverting 3-State | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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Philips Semiconductors Advanced BiCMOS Products
Octal latched transceiver with dual enable,
inverting (3-State)
Product specification
74ABT544
FEATURES
• Combines 74ABT245 and 74ABT373 type
functions in one device
• 8-bit octal transceiver with D-type latch
• Back-to-back registers for storage
• Separate controls for data flow in each
direction
• Output capability: +64mA/–32mA
• Live insertion/extraction permitted
• Power-up 3-State
• Power-up reset
• Latch-up protection exceeds 500mA per
Jedec JC40.2 Std 17
• ESD protection exceeds 2000 V per MIL
STD 883 Method 3015 and 200 V per
Machine Model
DESCRIPTION
The 74ABT544 high-performance BiCMOS
device combines low static and dynamic
power dissipation with high speed and high
output drive.
The 74ABT544 Octal Registered Transceiver
contains two sets of D-type latches for
temporary storage of data flowing in either
direction. Separate Latch Enable (LEAB,
LEBA) and Output Enable (OEAB, OEBA)
inputs are provided for each register to
permit independent control of data transfer in
either direction. The outputs are guaranteed
to sink 64mA.
FUNCTIONAL DESCRIPTION
The ’ABT544 contains two sets of eight
D–type latches, with separate control pins for
each set. Using data flow from A to B as an
example, when the A-to-B Enable (EAB)
input and the A-to-B Latch Enable (LEAB)
input are Low the A-to-B path is transparent.
A subsequent Low-to-High transition of the
LEAB signal puts the A data into the latches
where it is stored and the B outputs no longer
change with the A inputs. With EAB and
OEAB both Low, the 3-State B output buffers
are active and invert the data present at the
outputs of the A latches.
Control of data flow from B to A is similar, but
using the EBA, LEBA, and OEBA inputs.
ORDERING INFORMATION
PACKAGES
24-pin plastic DIP
24-pin plastic SOL
24-pin plastic SSOP Type II
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
ORDER CODE
74ABT544N
74ABT544D
74ABT544DB
DRAWING NUMBER
0410D
0173D
1641A
PIN CONFIGURATION
LEBA 1
OEBA 2
A0 3
A1 4
A2 5
A3 6
A4 7
A5 8
A6 9
A7 10
EAB 11
GND 12
24 VCC
23 EBA
22 B0
21 B1
20 B2
19 B3
18 B4
17 B5
16 B6
15 B7
14 LEAB
13 OEAB
June 1, 1993
LOGIC SYMBOL
LOGIC SYMBOL (IEEE/IEC)
3 4 5 6 7 8 9 10
A0 A1 A2 A3 A4 A5 A6 A7
11 EAB
23 EBA
14 LEAB
1 LEBA
OEAB
OEBA
13
2
B0 B1 B2 B3 B4 B5 B6 B7
22 21 20 19 18 17 16 15
2 1EN3 (AB)
23 G1
1
1C5
13
2EN4 (BA)
11
G2
14
2C6
3
∇3
5D
4
5D ∇ 4
5
6
7
8
9
10
22
21
20
19
18
17
16
15
1 853–1610 09907
1 page  
Philips Semiconductors Advanced BiCMOS Products
Octal latched transceiver with dual enable,
inverting (3-State)
Product specification
74ABT544
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Tamb = +25°C
Tamb = –40°C
to +85°C
UNIT
Min Typ Max Min Max
VIK Input clamp voltage
VOH High-level output voltage
VOL
VRST
Low-level output voltage
Power-up output low
voltage3
VCC = 4.5V; IIK = –18mA
VCC = 4.5V; IOH = –3mA; VI = VIL or VIH
VCC = 5.0V; IOH = –3mA; VI = VIL or VIH
VCC = 4.5V; IOH = –32mA; VI = VIL or VIH
VCC = 4.5V; IOL = 64mA; VI = VIL or VIH
VCC = 5.5V; IO = 1mA; VI = GND or VCC
–0.9 –1.2
–1.2
2.5 3.2
2.5
3.0 3.7
3.0
2.0 2.3
2.0
0.42 0.55
0.55
0.13 0.55
0.55
V
V
V
V
V
V
II
IOFF
IPU/PD
IIH + IOZH
IIL + IOZL
ICEX
IO
ICCH
ICCL
ICCZ
∆ICC
Input leakage Control pins
current
Data pins
Power-off leakage current
Power-up/down 3-State
output current4
3-State output High current
3-State output Low current
Output high leakage current
Output current1
Quiescent supply current
Additional supply current per
input pin2
VCC = 5.5V; VI = GND or 5.5V
VCC = 5.5V; VI = GND or 5.5V
VCC = 0.0V; VI or VO ≤ 4.5V
VCC = 2.1V; VO = 0.5V; VI = GND or VCC;
VOE = Don’t care
VCC = 5.5V; VO = 2.7V; VI = VIL or VIH
VCC = 5.5V; VO = 0.5V; VI = VIL or VIH
VCC = 5.5V; VO = 5.5V; VI = GND or VCC
VCC = 5.5V; VO = 2.5V
VCC = 5.5V; Outputs High, VI = GND or VCC
VCC = 5.5V; Outputs Low, VI = GND or VCC
VCC = 5.5V; Outputs 3–State;
VI = GND or VCC
VCC = 5.5V; one input at 3.4V,
other inputs at VCC or GND; VCC = 5.5V
±0.01
±5
±5.0
±1.0
±100
±100
±1.0
±100
±100
µA
µA
µA
±5.0 ±50
±50 µA
5.0 50
50 µA
–5.0 –50
–50 µA
5.0 50
50 µA
–50 –65 –180 –50 –180 mA
110 250
250 µA
20 30
30 mA
110 250
250 µA
0.3 1.5
1.5 mA
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip–flops (or latches) after applying the power.
4. This parameter is valid for any VCC between 0V and 2.1V, with a transition of 10msec. From VCC = 2.1V to VCC = 5V ± 10%, a transition
time of up to 100µsec is permitted.
June 1, 1993
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet 74ABT544.PDF ] | |
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