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PDF 74ABT374APWDH Data sheet ( Hoja de datos )
| Número de pieza | 74ABT374APWDH | |
| Descripción | Octal D-type flip-flop; positive-edge trigger 3-State | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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Philips Semiconductors
Octal D-type flip-flop; positive-edge trigger
(3-State)
Product specification
74ABT374A
FEATURES
• 8-bit positive edge triggered register
• 3-State output buffers
• Output capability: +64mA/–32mA
• Latch-up protection exceeds 500mA per Jedec Std 17
• ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
• Power-up 3-State
• Power-up reset
• Live insertion/extraction permitted
DESCRIPTION
The 74ABT374A high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
The 74ABT374A is an 8-bit, edge triggered register coupled to eight
3-State output buffers. The two sections of the device are controlled
independently by the clock (CP) and Output Enable (OE) control
gates.
The register is fully edge triggered. The state of each D input, one
set-up time before the Low-to-High clock transition, is transferred to
the corresponding flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active-Low Output Enable (OE) controls all eight 3-State buffers
independent of the clock operation.
When OE is Low, the stored data appears at the outputs. When OE
is High, the outputs are in the High-impedance “OFF” state, which
means they will neither drive nor load the bus.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
tPLH
tPHL
CIN
COUT
ICCZ
Propagation delay
CP to Qn
Input capacitance
Output capacitance
Total supply current
CONDITIONS
Tamb = 25°C; GND = 0V
CL = 50pF; VCC = 5V
VI = 0V or VCC
Outputs disabled; VO = 0V or VCC
Outputs disabled; VCC =5.5V
TYPICAL
3.4
3.8
4
7
110
UNIT
ns
pF
pF
µA
ORDERING INFORMATION
PACKAGES
20-Pin Plastic DIP
20-Pin plastic SO
20-Pin Plastic SSOP Type II
20-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74ABT374A N
74ABT374A D
74ABT374A DB
74ABT374A PW
NORTH AMERICA
74ABT374A N
74ABT374A D
74ABT374A DB
74ABT374APW DH
DWG NUMBER
SOT146-1
SOT163-1
SOT339-1
SOT360-1
PIN CONFIGURATION
OE 1
Q0 2
D0 3
D1 4
Q1 5
Q2 6
D2 7
D3 8
Q3 9
GND 10
20 VCC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 CP
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
FUNCTION
1 OE Output enable input (active-Low)
3, 4, 7, 8,
13, 14, 17,
18
D0-D7 Data inputs
2, 5, 6, 9,
12, 15, 16,
19
Q0-Q7 Data outputs
11 CP Clock pulse input (active rising edge)
10 GND Ground (0V)
20 VCC Positive supply voltage
SA00110
1995 Sep 06
1 853-1448 15704
1 page  
Philips Semiconductors
Octal D-type flip-flop; positive-edge trigger
(3-State)
Product specification
74ABT374A
AC SETUP REQUIREMENTS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω
SYMBOL
PARAMETER
WAVEFORM
ts(H)
ts(L)
th(H)
th(L)
tw(H)
tw(L)
Setup time, High or Low
Dn to CP
Hold time, High or Low
Dn to CP
CP pulse width
High or Low
2
2
1
AC WAVEFORMS
VM = 1.5V, VIN = GND to 3.0V
1/fMAX
CP VM VM
VM
tw(H)
tPHL
tw(L)
tPLH
Qn VM
VM
SA00056
Waveform 1. Propagation Delay, Clock Input to Output, Clock
Pulse Width, and Maximum Clock Frequency
ÉÉÉ ÉÉÉÉÉÉÉÉÉÉDn VM
ÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉts(H)
VM
th(H)
VM
ts(L)
VM
th(L)
CP
VM
VM
NOTE: The shaded areas indicate when the input is permitted
to change for predictable output performance.
Waveform 2. Data Setup and Hold Times
SA00107
LIMITS
Tamb = +25oC
VCC = +5.0V
Min Typ
Tamb = -40 to +85oC
VCC = +5.0V ±0.5V
Min
1.5 0.6
1.2 0.3
1.5
1.2
1.0 –0.3
1.0 –0.5
1.0
1.0
2.0 0.8
2.8 1.0
2.0
2.8
UNIT
ns
ns
ns
OE VM VM
tPZH
tPHZ
Qn VM VOH–0.3V
0V
SA00066
Waveform 3. 3-State Output Enable Time to High Level and
Output Disable Time from High Level
OE VM VM
tPZL
tPLZ
Qn VM VOL+0.3V
0V
SA00067
Waveform 4. 3-State Output Enable Time to Low Level and
Output Disable Time from Low Level
1995 Sep 06
5
5 Page | ||
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| PDF Descargar | [ Datasheet 74ABT374APWDH.PDF ] | |
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