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PDF 74ABT374 Data sheet ( Hoja de datos )

Número de pieza 74ABT374
Descripción Octal D-Type Flip-Flop with 3-STATE Outputs
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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No Preview Available ! 74ABT374 Hoja de datos, Descripción, Manual

December 2007
74ABT374
Octal D-Type Flip-Flop with 3-STATE Outputs
Features
Edge-triggered D-type inputs
Buffered positive edge-triggered clock
3-STATE outputs for bus-oriented applications
Output sink capability of 64mA, source capability of
32mA
Guaranteed output skew
Guaranteed multiple output switching specifications
Output switching specified for both 50pF and 250pF
loads
Guaranteed simultaneous switching, noise level and
dynamic threshold performance
Guaranteed latchup protection
High-impedance, glitch-free bus loading during entire
power up and power down cycle
Nondestructive, hot-insertion capability
General Description
The ABT374 is an octal D-type flip-flop featuring sepa-
rate D-type inputs for each flip-flop and 3-STATE outputs
for bus-oriented applications. A buffered Clock (CP) and
Output Enable (OE) are common to all flip-flops.
Ordering Information
Order Number
74ABT374CSC
74ABT374CSJ
74ABT374CMSA
74ABT374CMTC
Package
Number
M20B
M20D
MSA20
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013,
0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150,
5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC
MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1992 Fairchild Semiconductor Corporation
74ABT374 Rev. 1.5.0
www.fairchildsemi.com

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74ABT374 pdf
DC Electrical Characteristics
SOIC package.
Symbol
Parameter
VOLP
VOLV
VOHV
Quiet Output Maximum Dynamic VOL
Quiet Output Minimum Dynamic VOL
Minimum HIGH Level Dynamic Output
Voltage
VIHD
Minimum HIGH Level Dynamic Input
Voltage
VILD Maximum LOW Level Dynamic Input
Voltage
VCC
5.0
5.0
5.0
Conditions
CL = 50pF,
RL = 500
TA = 25°C(4)
TA = 25°C(4)
TA = 25°C(5)
5.0 TA = 25°C(6)
5.0 TA = 25°C(6)
Min.
–1.3
2.5
Typ.
0.5
–0.9
3.0
Max. Units
0.8 V
V
V
2.0 1.6
V
1.3 0.8
V
Notes:
4. Max number of outputs defined as (n). n – 1 data inputs are driven 0V to 3V. One output at Low. Guaranteed, but not
tested.
5. Max number of outputs defined as (n). n – 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not
tested.
6. Max number of data inputs (n) switching. n – 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold
(VILD), 0V to threshold (VIHD). Guaranteed, but not tested.
AC Electrical Characteristics
SOIC and SSOP package.
Symbol
Parameter
TA = +25°C,
VCC = +5V,
CL = 50pF
TA = –55°C to +125°C, TA = –40°C to +85°C,
VCC = 4.5V to 5.5V, VCC = 4.5V to 5.5V,
CL = 50pF
CL = 50pF
Min. Typ. Max. Min.
Max.
Min.
Max. Units
fMAX Maximum Clock
Frequency
150 200
150
150 MHz
tPLH Propagation Delay 2.0 3.2 5.0
1.4
6.6
2.0 5.0 ns
tPHL CP to On
2.0 3.3 5.0
2.0
7.6
2.0 5.0
tPZH Output Enable Time 1.5 3.1 5.3
0.8
5.7
1.5 5.3 ns
tPZL
1.5 3.1 5.3
1.5
7.2
1.5 5.3
tPHZ Output Disable Time 1.5 3.6 5.4
1.3
7.2
1.5 5.4 ns
tPLZ
1.5 3.4 5.4
1.0
7.0
1.5 5.4
©1992 Fairchild Semiconductor Corporation
74ABT374 Rev. 1.5.0
5
www.fairchildsemi.com

5 Page





74ABT374 arduino
Physical Dimensions (Continued)
Figure 10. 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1992 Fairchild Semiconductor Corporation
74ABT374 Rev. 1.5.0
11
www.fairchildsemi.com

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