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PDF 74ABT273CSC Data sheet ( Hoja de datos )
| Número de pieza | 74ABT273CSC | |
| Descripción | Octal D-Type Flip-Flop | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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January 1993
Revised November 1999
74ABT273
Octal D-Type Flip-Flop
General Description
The ABT273 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) and Master Reset (MR) inputs load and reset
(clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D
input, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only
is required and the Clock and Master Reset are common to
all storage elements.
Features
s Eight edge-triggered D-type flip-flops
s Buffered common clock
s Buffered, asynchronous Master Reset
s See ABT377 for clock enable version
s See ABT373 for transparent latch version
s See ABT374 for 3-STATE version
s Output sink capability of 64 mA, source capability of
32 mA
s Guaranteed latchup protection
s High impedance glitch free bus loading during entire
power up and power down cycle
s Non-destructive hot insertion capability
s Disable time less than enable time to avoid bus conten-
tion
Ordering Code:
Order Number Package Number
Package Description
74ABT273CSC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ABT273CSJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ABT273CMSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74ABT273CMTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
D0–D7
MR
CP
Q0–Q7
Description
Data Inputs
Master Reset (Active LOW)
Clock Pulse Input (Active Rising Edge)
Data Outputs
© 1999 Fairchild Semiconductor Corporation DS011549
www.fairchildsemi.com
1 page  
AC Loading
*Includes jig and probe capacitance
FIGURE 1. Standard AC Test Load
FIGURE 2. VM = 1.5V
Input Pulse Requirements
AC Waveforms
Amplitude Rep. Rate
tW
tr
tf
3.0V
1 MHz 500 ns 2.5 ns 2.5 ns
FIGURE 3. Test Input Signal Requirements
FIGURE 4. Propagation Delay,
Pulse Width Waveforms
FIGURE 6. Propagation Delay Waveforms for
Inverting and Non-Inverting Functions
FIGURE 5. 3-STATE Output HIGH
and LOW Enable and Disable Times
FIGURE 7. Setup Time, Hold Time
and Recovery Time Waveforms
5 www.fairchildsemi.com
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet 74ABT273CSC.PDF ] | |
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