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PDF 74ABT245CMTC Data sheet ( Hoja de datos )
| Número de pieza | 74ABT245CMTC | |
| Descripción | Octal Bi-Directional Transceiver with 3-STATE Outputs | |
| Fabricantes | Fairchild Semiconductor | |
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September 1991
Revised November 1999
74ABT245
Octal Bi-Directional Transceiver with 3-STATE Outputs
General Description
The ABT245 contains eight non-inverting bidirectional buff-
ers with 3-STATE outputs and is intended for bus-oriented
applications. Current sinking capability is 64 mA on both
the A and B ports. The Transmit/Receive (T/R) input deter-
mines the direction of data flow through the bidirectional
transceiver. Transmit (active HIGH) enables data from A
Ports to B Ports; Receive (active LOW) enables data from
B Ports to A Ports. The Output Enable input, when HIGH,
disables both A and B ports by placing them in a HIGH Z
condition.
Features
s Bidirectional non-inverting buffers
s A and B output sink capability of 64 mA, source
capability of 32 mA
s Guaranteed output skew
s Guaranteed multiple output switching specifications
s Output switching specified for both 50 pF and 250 pF
loads
s Guaranteed simultaneous switching, noise level and
dynamic threshold performance
s Guaranteed latchup protection
s High impedance glitch-free bus loading during entire
power up and power down cycle
s Non-destructive hot insertion capability
s Disable time is less than enable time to avoid bus
contention
Ordering Code:
Order Number Package Number
Package Description
74ABT245CSC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ABT245CSJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ABT245CMSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74ABT245CMTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ABT245CPC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
OE
T/R
A0–A7
B0–B7
Description
Output Enable Input (Active LOW)
Transmit/Receive Input
Side A Inputs or 3-STATE Outputs
Side B Inputs or 3-STATE Outputs
© 1999 Fairchild Semiconductor Corporation DS010945
www.fairchildsemi.com
1 page  
Skew
(SOIC package)
TA = −40°C to +85°C
TA = −40°C to +85°C
VCC = 4.5V–5.5V
VCC = 4.5V–5.5V
Symbol
Parameter
CL = 50 pF
8 Outputs Switching
CL = 250 pF
8 Outputs Switching
Units
(Note 12)
(Note 13)
Max
Max
tOSHL
(Note 10)
Pin to Pin Skew
HL Transitions
1.3 2.3 ns
tOSLH
(Note 10)
Pin to Pin Skew
LH Transitions
1.0 1.8 ns
tPS
(Note 14)
Duty Cycle
LH–HL Skew
2.0 3.5 ns
tOST
(Note 10)
Pin to Pin Skew
LH/HL Transitions
2.0 3.5 ns
tPV
(Note 11)
Device to Device Skew
LH/HL Transitions
2.0 3.5 ns
Note 10: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or
HIGH-to-LOW (tOST). The specification is guaranteed but not tested.
Note 11: Propagation delay variation for a given set of conditions (i.e., temperature and VCC) from device to device. This specification is guaranteed but not
tested.
Note 12: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.)
Note 13: These specifications guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load.
Note 14: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all
the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested.
Capacitance
Symbol
Parameter
Typ
CIN Input Capacitance
5.0
CI/O (Note 15)
I/O Capacitance
11.0
Note 15: CI/O is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
Units
pF
pF
Conditions
TA = 25°C
VCC = 0V (OE, T/R)
VCC = 5.0V (An, Bn)
5 www.fairchildsemi.com
5 Page 
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
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