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PDF 74ABT16501 Data sheet ( Hoja de datos )
| Número de pieza | 74ABT16501 | |
| Descripción | 18-Bit Universal Bus Transceivers with 3-STATE Outputs | |
| Fabricantes | Fairchild Semiconductor | |
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January 1995
Revised January 1999
74ABT16501
18-Bit Universal Bus Transceivers with 3-STATE Outputs
General Description
The ABT16501 18-bit universal bus transceiver combines
D-type latches and D-type flip-flops to allow data flow in
transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the
device operates in the transparent mode when LEAB is
HIGH. When LEAB is LOW, the A data is latched if CLKAB
is held at a HIGH or LOW logic level. If LEAB is LOW, the A
bus data is stored in the latch/flip-flop on the LOW-to-HIGH
transition of CLKAB. Output-enable OEAB is active-high.
When OEAB is HIGH, the outputs are active. When OEAB
is LOW, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B but uses
OEBA, LEBA, and CLKBA. The output enables are com-
plementary (OEAB is active HIGH and OEBA is active
LOW).
To ensure the high-impedance state during power up or
power down, OE inputs should be tied to GND through a
pulldown resistor; the minimum value of the resistor is
determined by the current-sourcing capability of the driver.
Features
s Combines D-Type latches and D-Type flip-flops for oper-
ation in transparent, latched, or clocked mode
s Flow-through architecture optimizes PCB layout
s Guaranteed latch-up protection
s High impedance glitch free bus loading during entire
power up and power down cycle
s Non-destructive hot insertion capability
Ordering Code:
Order Number Package Number
Package Description
74ABT16501CSSC
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74ABT16501CMTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape or Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignment for SSOP
Function Table (Note 1)
Inputs
Output
OEAB LEAB CLKAB A
B
LXXX
Z
HHX L
L
HHXH
H
HL ↑L
L
HL ↑H
H
H L H X B0 (Note 2)
H L L X B0 (Note 3)
Note 1: A-to-B data flow is shown: B-to-A flow is similar but uses OEBA,
LEBA, and CLKBA.
Note 2: Output level before the indicated steady-state input conditions
were established.
Note 3: Output level before the indicated steady-state input conditions
were established, provided that CLKAB was HIGH before LEAB went LOW.
© 1999 Fairchild Semiconductor Corporation DS011690.prf
www.fairchildsemi.com
1 page  
Capacitance
Symbol
Parameter
Typ
CIN Input Capacitance
5.0
CI/O (Note 10)
Output Capacitance
11.0
Note 10: CI/O is measured at frequency f = 1 MHz per MIL-STD-883, Method 3012.
AC Loading
Units
pF
pF
VCC = 0.0V
VCC = 5.0V
Conditions
TA = 25°C
*Includes jig and probe capacitance.
FIGURE 1. Standard AC Test Load
FIGURE 2. VM = 1.5V
Input Pulse Requirements
Amplitude Rep. Rate
tW
tr
tf
3.0V
1 MHz 500 ns 2.5 ns 2.5 ns
FIGURE 3. Test Input Signal Requirements
AC Waveforms
FIGURE 4. Propagation Delay Waveforms
for Inverting and Non-Inverting Functions
FIGURE 6. 3-STATE Output HIGH
and LOW Enable and Disable Times
FIGURE 5. Propagation Delay,
Pulse Width Waveforms
FIGURE 7. Setup Time, Hold Time
and Recovery Time Waveforms
5 www.fairchildsemi.com
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| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet 74ABT16501.PDF ] | |
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