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PDF HYB25D256800BT Data sheet ( Hoja de datos )
| Número de pieza | HYB25D256800BT | |
| Descripción | 256MBit Double Data Rata SDRAM | |
| Fabricantes | Infineon Technologies AG | |
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HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum Jan. 2003, V0.9
Features
CAS Latency and Clock Frequency
CAS Latency
2
2.5
3
Maximum Operating Frequency (MHz)
DDR400B
-5
DDR400A
-5A
133 133
166 200
200 200
• Double data rate architecture: two data transfers
per clock cycle
• Bidirectional data strobe (DQS) is transmitted
and received with data, to be used in capturing
data at the receiver
• DQS is edge-aligned with data for reads and is
center-aligned with data for writes
• Differential clock inputs (CK and CK)
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge;
data and data mask referenced to both edges of
DQS
• Burst Lengths: 2, 4, or 8
• CAS Latency: (1.5), 2, 2.5, (3)
• Auto Precharge option for each burst access
• Auto Refresh and Self Refresh Modes
• 7.8ms Maximum Average Periodic Refresh
Interval (8k refresh)
• 2.5V (SSTL_2 compatible) I/O
• VDDQ = 2.6V ± 0.1V / VDD = 2.6V ± 0.1V
• TSOP66 package
Description
The 256Mb DDR SDRAM is a high-speed CMOS,
dynamic random-access memory containing 268,435,456
bits. It is internally configured as a quad-bank DRAM.
The 256Mb DDR SDRAM uses a double-data-rate archi-
tecture to achieve high-speed operation. The double data
rate architecture is essentially a 2n prefetch architecture
with an interface designed to transfer two data words per
clock cycle at the I/O pins. A single read or write access
for the 256Mb DDR SDRAM effectively consists of a sin-
gle 2n-bit wide, one clock cycle data transfer at the inter-
nal DRAM core and two corresponding n-bit wide, one-
half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver.
DQS is a strobe transmitted by the DDR SDRAM during
Reads and by the memory controller during Writes. DQS
is edge-aligned with data for Reads and center-aligned
with data for Writes.
The 256Mb DDR SDRAM operates from a differential
clock (CK and CK; the crossing of CK going HIGH and CK
going LOW is referred to as the positive edge of CK).
Commands (address and control signals) are registered at
every positive edge of CK. Input data is registered on both
edges of DQS, and output data is referenced to both
edges of DQS, as well as to both edges of CK.
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and con-
tinue for a programmed number of locations in a pro-
grammed sequence. Accesses begin with the registration
of an Active command, which is then followed by a Read
or Write command. The address bits registered coincident
with the Active command are used to select the bank and
row to be accessed. The address bits registered coinci-
2003-01-10, V0.9
dent with the Read or Write command are used to select
the bank and the starting column location for the burst
access.
The DDR SDRAM provides for programmable Read or
Write burst lengths of 2, 4 or 8 locations. An Auto Pre-
charge function may be enabled to provide a self-timed
row precharge that is initiated at the end of the burst
access.
As with standard SDRAMs, the pipelined, multibank archi-
tecture of DDR SDRAMs allows for concurrent operation,
thereby providing high effective bandwidth by hiding row
precharge and activation time.
An auto refresh mode is provided along with a power-sav-
ing power-down mode. All inputs are compatible with the
JEDEC Standard for SSTL_2. All outputs are SSTL_2,
Class II compatible.
Note: The functionality described and the timing specifi-
cations included in this data sheet are for the DLL Enabled
mode of operation.
Page 1 of 29
1 page  
Block Diagram (32Mb x 8)
HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
CKE
CK
CK
CS
WE
CAS
RAS
Mode
Registers
13
13
A0-A12,
BA0, BA1
15
2
2
10 Column-Address
Counter/Latch
Bank3
Bank1 Bank2
CK, CK
DLL
8192
Bank0
Memory
Array
(8192 x 512x 16)
Sense Amplifiers
I/O Gating
DM Mask Logic
512
(x16)
Column
Decoder
9
COL0
1
16
16
16
Data
8
8
8
DQS
Generator
COL0 Input
Register
Write Mask 1
1
FIFO
&
Drivers
1
2
16 8
1
8
clk
out
clk
in
Data
8
8
1
DQS
1
8
CK, COL0
CK
1
DQ0-DQ7,
DM
DQS
Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of
the device; it does not represent an actual circuit implementation.
Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi-
rectional DQ and DQS signals.
2003-01-10, V0.9
Page 5 of 29
5 Page 
HYB25D256[800/160]BT(L)-[5/5A]
256MBit Double Data Rata SDRAM
Preliminary DDR400 Data Sheet Addendum
Operating Mode
The normal operating mode is selected by issuing a Mode Register Set Command with bits A7-A12 set to
zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a Mode Register Set com-
mand with bits A7 and A9-A12 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values. A
Mode Register Set command issued to reset the DLL should always be followed by a Mode Register Set
command to select normal operating mode.
All other combinations of values for A7-A12 are reserved for future use and/or test modes. Test modes and
reserved states should not be used as unknown operation or incompatibility with future versions may result.
Required CAS Latencies
CK
CK
Command
DQS
DQ
Read
NOP
CL=2
NOP
CAS Latency = 2, BL = 4
NOP
NOP
NOP
CK
CK
Command
DQS
DQ
Read
NOP
CL=2.5
NOP
Shown with nominal tAC, tDQSCK, and tDQSQ.
CAS Latency = 2.5, BL = 4
NOP
NOP
NOP
Don’t Care
2003-01-10, V0.9
Page 11 of 29
11 Page | ||
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