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PDF HYB25D256400BT Data sheet ( Hoja de datos )
| Número de pieza | HYB25D256400BT | |
| Descripción | 256-Mbit Double Data Rate SDRAM/ Die Rev. B | |
| Fabricantes | Infineon Technologies AG | |
| Logotipo |  |
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HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Data Sheet Jan. 2003, V1.1
Features
CAS Latency and Frequency
CAS Latency
2
2.5
Maximum Operating Frequency (MHz)
DDR200 DDR266A DDR266 DDR333
-8 -7 -7F -6
100 133 133 133
125 143 143 166
• Double data rate architecture: two data transfers
per clock cycle
• Bidirectional data strobe (DQS) is transmitted
and received with data, to be used in capturing
data at the receiver
• DQS is edge-aligned with data for reads and is
center-aligned with data for writes
• Differential clock inputs (CK and CK)
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge;
data and data mask referenced to both edges of
DQS
• Burst Lengths: 2, 4, or 8
• CAS Latency: (1.5), 2, 2.5, (3)
• Auto Precharge option for each burst access
• Auto Refresh and Self Refresh Modes
• 7.8ms Maximum Average Periodic Refresh
Interval (8K refresh)
• 2.5V (SSTL_2 compatible) I/O
• VDDQ = 2.5V ± 0.2V / VDD = 2.5V ± 0.2V
• TSOP66 package
• 60 balls BGA w/ 3 depop rows (“chipsize pack-
age”) 12 mm x 8 mm.
Description
The 256Mb DDR SDRAM is a high-speed CMOS,
dynamic random-access memory containing 268,435,456
bits. It is internally configured as a quad-bank DRAM.
The 256Mb DDR SDRAM uses a double-data-rate archi-
tecture to achieve high-speed operation. The double data
rate architecture is essentially a 2n prefetch architecture
with an interface designed to transfer two data words per
clock cycle at the I/O pins. A single read or write access
for the 256Mb DDR SDRAM effectively consists of a sin-
gle 2n-bit wide, one clock cycle data transfer at the inter-
nal DRAM core and two corresponding n-bit wide, one-
half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver.
DQS is a strobe transmitted by the DDR SDRAM during
Reads and by the memory controller during Writes. DQS
is edge-aligned with data for Reads and center-aligned
with data for Writes.
The 256Mb DDR SDRAM operates from a differential
clock (CK and CK; the crossing of CK going HIGH and CK
going LOW is referred to as the positive edge of CK).
Commands (address and control signals) are registered at
every positive edge of CK. Input data is registered on both
edges of DQS, and output data is referenced to both
edges of DQS, as well as to both edges of CK.
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and con-
tinue for a programmed number of locations in a pro-
grammed sequence. Accesses begin with the registration
of an Active command, which is then followed by a Read
or Write command. The address bits registered coincident
with the Active command are used to select the bank and
row to be accessed. The address bits registered coinci-
dent with the Read or Write command are used to select
the bank and the starting column location for the burst
access.
The DDR SDRAM provides for programmable Read or
Write burst lengths of 2, 4 or 8 locations. An Auto Pre-
charge function may be enabled to provide a self-timed
row precharge that is initiated at the end of the burst
access.
As with standard SDRAMs, the pipelined, multibank archi-
tecture of DDR SDRAMs allows for concurrent operation,
thereby providing high effective bandwidth by hiding row
precharge and activation time.
An auto refresh mode is provided along with a power-sav-
ing power-down mode. All inputs are compatible with the
JEDEC Standard for SSTL_2. All outputs are SSTL_2,
Class II compatible.
Note: The functionality described and the timing specifi-
cations included in this data sheet are for the DLL Enabled
mode of operation.
2003-01-09, V1.1
Page 1 of 77
1 page  
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Input/Output Functional Description
Symbol
CK, CK
CKE
CS
RAS, CAS, WE
DM
BA0, BA1
A0 - A12
DQ
DQS
NC
VDDQ
VSSQ
VDD
VSS
VREF
Type
Input
Input
Input
Input
Input
Input
Input
Input/Output
Input/Output
Supply
Supply
Supply
Supply
Supply
Function
Clock: CK and CK are differential clock inputs. All address and control input signals are sam-
pled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data
is referenced to the crossings of CK and CK (both directions of crossing).
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and
device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down
and Self Refresh operation (all banks idle), or Active Power-Down (row Active in any bank).
CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is asyn-
chronous for self refresh exit. CKE must be maintained high throughout read and write
accesses. Input buffers, excluding CK, CK and CKE are disabled during power-down. Input
buffers, excluding CKE, are disabled during self refresh.
Chip Select: All commands are masked when CS is registered HIGH. CS provides for exter-
nal bank selection on systems with multiple banks. CS is considered part of the command
code. The standard pinout includes one CS pin.
Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM
is sampled HIGH coincident with that input data during a Write access. DM is sampled on
both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and
DQS loading.
Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or Pre-
charge command is being applied. BA0 and BA1 also determines if the mode register or
extended mode register is to be accessed during a MRS or EMRS cycle.
Address Inputs: Provide the row address for Active commands, and the column address
and Auto Precharge bit for Read/Write commands, to select one location out of the memory
array in the respective bank. A10 is sampled during a Precharge command to determine
whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one
bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide
the op-code during a Mode Register Set command.
Data Input/Output: Data bus.
Data Strobe: Output with read data, input with write data. Edge-aligned with read data, cen-
tered in write data. Used to capture write data.
No Connect: No internal electrical connection is present.
DQ Power Supply: 2.5V ± 0.2V.
DQ Ground
Power Supply: 2.5V ± 0.2V.
Ground
SSTL_2 reference voltage: (VDDQ / 2)
Page 5 of 77
2003-01-09, V1.1
5 Page 
HYB25D256[400/800/160]B[T/C](L)
256-Mbit Double Data Rate SDRAM, Die Rev. B
Mode Register Operation
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
0* 0*
Operating Mode
CAS Latency BT Burst Length
Mode Register
A12 - A9
0
0
0
-
A8 A7
00
10
01
--
A6 - A0
Valid
Valid
Operating Mode
Normal operation
Do not reset DLL
Normal operation
in DLL Reset
Reserved
Reserved
A3 Burst Type
0 Sequential
1 Interleave
CAS Latency
A6 A5 A4
000
001
010
011
100
101
110
111
Latency
Reserved
Reserved
2
3 (optional)
Reserved
1.5 (optional)
2.5
Reserved
Burst Length
A2 A1 A0 Burst Length
000
Reserved
001
2
010
4
011
8
100
Reserved
101
Reserved
110
Reserved
111
Reserved
* BA0 and BA1 must be 0, 0 to select the Mode Register
(vs. the Extended Mode Register).
Page 11 of 77
2003-01-09, V1.1
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HYB25D256400BT.PDF ] | |
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