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PDF HYB18T256800AF Data sheet ( Hoja de datos )

Número de pieza HYB18T256800AF
Descripción 256 Mbi t DDR2 SDRAM
Fabricantes Infineon Technologies AG 
Logotipo Infineon Technologies AG Logotipo



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No Preview Available ! HYB18T256800AF Hoja de datos, Descripción, Manual

Data Sheet, V1.02, May 2004
HYB18T256400AF
HYB18T256800AF
HYB18T256160AF
256 Mbit DDR2 SDRAM
Memory Products
Never stop thinking.

1 page




HYB18T256800AF pdf
1.2.1 x8 Components
Symbol
A0~A12
A0~A9
BA0, BA1
A10/AP
CS
RAS
CAS
WE
DQ0~DQ7
CKE
CK, CK
DM
Function
Row Address Inputs
Column Address Inputs
Bank Address Inputs
Column Address Input
for Auto-Precharge
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Data Inputs/Outputs (x8)
Clock Enable
Differential Clock Inputs
Data Input Mask
1.2.3 x16 Components
Symbol
A0~A12
A0~A8
BA0, BA1
A10/AP
CS
RAS
CAS
WE
LDQ0~7, UDQ0~7
CKE
CK, CK
LDM, UDM
Function
Row Address Inputs
Column Address Inputs
Bank Address Inputs
Column Address Input
for Auto-Precharge
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Data Inputs/Outputs
Clock Enable
Differential Clock Inputs
Data Input Masks
HYB18T256400/800/160AF
256Mb DDR2 SDRAM
Symbol
DQS, DQS
RDQS, RDQS
VDD
VSS
VDDQ
VSSQ
VDDL
VSSDL
VREF
ODT
RFU
NC
Function
Differential Data Strobes
Differential Read Data Strobes
Supply Voltage
Ground
Supply Voltage for DQ
Ground for DQs
Supply Voltage for DLL
Ground for DLL
Reference Voltage for SSTL
Inputs
On Die Termination Enable
Reserved for future use
Not connected
Symbol
LDQS,LDQS
UDQS,UDQS
NC
VDD
VSS
VDDQ
VSSQ
VDDL
VSSDL
VREF
ODT
RFU
NC
Function
Differential Data Strobes
No Connection (Chip to Pin)
Supply Voltage
Ground
Supply Voltage for DQ
Ground for DQs
Supply Voltage for DLL
Ground for DLL
Reference Voltage for SSTL
Inputs
On Die Termination Enable
reserved for future use
Not connected
Page 5
Rev. 1.02 May 2004
INFINEON Technologies

5 Page





HYB18T256800AF arduino
HYB18T256400/800/160AF
256Mb DDR2 SDRAM
CKE
CK
CK
CS
WE
CAS
RAS
AP
Mode
Registers
15
15
15
A0-A12,
BA0, BA1
15
2
2
10 Column-Address
Counter/Latch
Bank3
Bank1 Bank2
CK, CK
DLL
8192
Bank0
Memory
Array
(8192x256x32)
Sense Amplifiers
I/O Gating
DM Mask Logic
256
(x32)
Column
Decoder
8
COL0,1
2
Data
32
32
32
8
88
8
8 DQS
Generator
COL0,1 Input
Register
Write Mask 1
1
FIFO
&
Drivers
1
1
4
1
1
1
1
1
DQS
DQS
1
88
8
32
8
Data 8
8
8
8
8
CK,
CK
COL0,1
DQ0-DQ7,
DM
DQS
DQS
Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of
the device; it does not represent an actual circuit implementation.
Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi-
rectional DQ and DQS signals.
Block Diagram 8Mbit x 8 I/O x 4 Internal Memory Banks
(32Mb x 8 Organisation with 13 Row, 2 Bank and 10 Column External Addresses)
Page 11
Rev. 1.02 May 2004
INFINEON Technologies

11 Page







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