PDF HYB18T1G800AF Data sheet ( Hoja de datos )

Número de pieza	HYB18T1G800AF
Descripción	1 Gbit DDR2 SDRAM
Fabricantes	Infineon Technologies AG
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No Preview Available ! Data Sheet, V1.02, May 2004 HYB18T1G400AF HYB18T1G800AF HYB18T1G160AF 1 Gbit DDR2 SDRAM Memory Products Never stop thinking. 1 page 1.2.1 x8 Components Symbol A0~A13 A0~A9 BA0, BA1, BA2 A10/AP CS RAS CAS WE DQ0~DQ7 CKE CK, CK DM Function Row Address Inputs Column Address Inputs Bank Address Inputs Column Address Input for Auto-Precharge Chip Select Row Address Strobe Column Address Strobe Write Enable Data Inputs/Outputs (x8) Clock Enable Differential Clock Inputs Data Input Mask 1.2.3 x16 Components Symbol A0~A12 A0~A9 BA0, BA1, BA2 A10/AP CS RAS CAS WE LDQ0~7, UDQ0~7 CKE CK, CK LDM, UDM Function Row Address Inputs Column Address Inputs Bank Address Inputs Column Address Input for Auto-Precharge Chip Select Row Address Strobe Column Address Strobe Write Enable Data Inputs/Outputs Clock Enable Differential Clock Inputs Data Input Masks HYB18T1G400/800/160AF 1Gb DDR2 SDRAM Symbol DQS, DQS RDQS, RDQS VDD VSS VDDQ VSSQ VDDL VSSDL VREF ODT NC Function Differential Data Strobes Differential Read Data Strobes Supply Voltage Ground Supply Voltage for DQ Ground for DQs Supply Voltage for DLL Ground for DLL Reference Voltage for SSTL Inputs On Die Termination Enable Not connected Symbol LDQS,LDQS UDQS,UDQS NC VDD VSS VDDQ VSSQ VDDL VSSDL VREF ODT NC Function Differential Data Strobes No Connection (Chip to Pin) Supply Voltage Ground Supply Voltage for DQ Ground for DQs Supply Voltage for DLL Ground for DLL Reference Voltage for SSTL Inputs On Die Termination Enable Not connected Page 5 Rev. 1.02 May 2004 INFINEON Technologies 5 Page HYB18T1G400/800/160AF 1Gb DDR2 SDRAM CKE CK CK CS WE CAS RAS AP A0-A13, BA0-BA2 Bank1 Bank0 Bank7 CK, CK Mode Registers 17 17 17 2 17 2 10 Column-Address Counter/Latch 16384 Bank0 Memory Array (16384 x256x32) Sense Amplifiers 8 I/O Gating DM Mask Logic 8 256 (x32) Column Decoder 8 COL0,1 2 DLL Data 32 32 32 8 88 8 8 DQS Generator COL0,1 Input Register Write Mask 1 1 FIFO & Drivers 1 1 4 1 1 1 1 1 DQS DQS 1 88 8 32 8 Data 8 8 8 8 8 CK, CK COL0,1 DQ0-DQ7, DM DQS DQS Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi- rectional DQ and DQS signals. Block Diagram 32Mbit x 8 I/O x 4 Internal Memory Banks (64Mb x 8 Organisation with 14 Row, 3 Bank and 11 Column External Addresses) Page 11 Rev. 1.02 May 2004 INFINEON Technologies 11 Page

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Número de pieza	Descripción	Fabricantes
HYB18T1G800AF	1 Gbit DDR2 SDRAM	Infineon Technologies AG

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