IDT54FCT273TD Datasheet PDF - Integrated Device Technology
| Part Number | IDT54FCT273TD | |
| Description | FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET | |
| Manufacturers | Integrated Device Technology | |
| Logo |  |
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Integrated Device Technology, Inc.
FAST CMOS
OCTAL D FLIP-FLOP
WITH MASTER RESET
IDT54/74FCT273T/AT/CT
FEATURES:
• Std., A, and C speed grades
• Low input and output leakage ≤1µA (max.)
• CMOS power levels
• True TTL input and output compatibility
– VOH = 3.3V (typ.)
– VOL = 0.3V (typ.)
• High drive outputs (-15mA IOH, 48mA IOL)
• Meets or exceeds JEDEC standard 18 specifications
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
and DESC listed (dual marked)
• Available in DIP, SOIC, QSOP, CERPACK and LCC
packages
DESCRIPTION:
The IDT54/74FCT273T/AT/CT are octal D flip-flops built
using an advanced dual metal CMOS technology. The IDT54/
74FCT273T/AT/CT have eight edge-triggered D-type flip-
MRflops with individual D inputs and O outputs. The common
buffered Clock (CP) and Master Reset ( ) inputs load and
reset (clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D
input, one set-up time before the LOW-to-HIGH clock
transition, is transferred to the corresponding flip-flop’s O
output.
MRAll outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the input. The
device is useful for applications where the true output only is
required and the Clock and Master Reset are common to all
storage elements.
FUNCTIONAL BLOCK DIAGRAM
D0 D1 D2 D3 D4 D5 D6 D7
CP
DQ
CP
RD
DQ
CP
RD
DQ
CP
RD
DQ
CP
RD
DQ
CP
RD
DQ
CP
RD
DQ
CP
RD
DQ
CP
RD
MR
O0 O1 O2 O3
PIN CONFIGURATIONS
MR
O0
D0
D1
O1
O2
D2
D3
O3
GND
1 20
2 19
3 18
4
P20-1
D20-1
17
5 SO20-2 16
6 SO20-8 15
7
&
E20-1
14
8 13
9 12
10 11
VCC
O7
D7
D6
O6
O5
D5
D4
O4
CP
2568 drw 01
DIP/SOIC/QSOP/CERPACK
TOP VIEW
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1995 Integrated Device Technology, Inc.
6.10
O4
INDEX
D1
O1
O2
D2
D3
O5 O6 O7
2568 drw 03
3 2 20 19
4 1 18
5 17
6 L20-2 16
7 15
8 14
9 10 11 12 13
D7
D6
O6
O5
D5
LCC
TOP VIEW
2568 drw 02
APRIL 1995
DSC-4209/3
1
|
| |
 
IDT54/74FCT273T/AT/CT FAST CMOS
OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT273T IDT54/74FCT273AT IDT54/74FCT273CT
Com'l. Mil. Com'l. Mil. Com'l. Mil.
Symbol
Parameter
tPLH Propagation Delay
tPHL CP to ON
tPHL Propagation Delay
MR to ON
tSU Set-up Time HIGH or LOW
DN to CP
tH Hold Time HIGH or LOW DN
to CP
tW CP Pulse Width HIGH or
LOW
tW MR Pulse Width LOW
Condition(1)
CL = 50pF
RL = 500Ω
Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max.
2.0 13.0 2.0 15.0 2.0 7.2 2.0 8.3 2.0 5.8 2.0 6.5
Unit
ns
2.0 13.0 2.0 15.0 2.0 7.2 2.0 8.3 2.0 6.1 2.0 6.8 ns
3.0 — 3.5 — 2.0 — 2.0 — 2.0 — 2.0 — ns
2.0 — 2.0 — 1.5 — 1.5 — 1.5 — 1.5 — ns
7.0 — 7.0 — 6.0 — 6.0 — 6.0 — 6.0 — ns
7.0 — 7.0 — 6.0 — 6.0 — 6.0 — 6.0 — ns
tREM Recovery Time MR
to CP
4.0 — 5.0 — 2.0 — 2.5 — 2.0 — 2.5 — ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
2568 tbl 07
6.10 5
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| Information | Total 7 Pages | |
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