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PDF IDT54FCT273T Data sheet ( Hoja de datos )
| Número de pieza | IDT54FCT273T | |
| Descripción | FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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IDT54/74FCT273T/AT/CT
FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARYANDINDUSTRIALTEMPERATURERANGES
FAST CMOS
OCTAL D FLIP-FLOP
WITH MASTER RESET
IDT54/74FCT273T/AT/CT
FEATURES:
• Std., A, and C grades
• Low input and output leakage ≤1µA (max.)
• CMOS power levels
• True TTL input and output compatibility:
– VOH = 3.3V (typ.)
– VOL = 0.3V (typ.)
• High Drive outputs (-15mA IOH, 48mA IOL)
• Meets or exceeds JEDEC standard 18 specifications
• Military product compliant to MIL-STD-883, Class B and DESC
listed (dual marked)
• Power off disable outputs permit "live insertion"
• Available in the following packages:
– Industrial: SOIC, SSOP, QSOP
– Military: CERDIP, LCC
DESCRIPTION:
The FCT273T is an octal D flip-flop built using an advanced dual metal
CMOS technology. The FCT273T has eight edge-triggered D-type flip-
flops with individual D inputs and O outputs. The common buffered Clock
(CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops
simultaneously.
The register is fully edge-triggered. The state of each D input, one set-
up time before the low-to-high clock transition, is transferred to the corre-
sponding flip-flop’s O output.
All outputs will be forced low independently of Clock or Data inputs by
a low voltage level on the MR input. The device is useful for applications
where the true output only is required and the Clock and Master Reset are
common to all storage elements.
FUNCTIONAL BLOCK DIAGRAM
D0 D1 D2 D3 D4 D5 D6 D7
CP
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CP CP CP CP CP CP CP CP
RD RD RD RD RD RD RD RD
MR
O0 O1 O2 O3 O4 O5 O6 O7
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
1
© 2002 Integrated Device Technology, Inc.
JUNE 2002
DSC-2568/2
1 page  
IDT54/74FCT273T/AT/CT
FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARYANDINDUSTRIALTEMPERATURERANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE - INDUSTRIAL
Symbol
tPLH
tPHL
tPLH
tPHL
tSU
tH
tW
tW
tREM
Parameter
Propagation Delay
CP to Ox
Propagation Delay
MR to Ox
Set-up Time HIGH or LOW
Dx to CP
Hold Time HIGH or LOW
Dx to CP
CP Pulse Width HIGH or LOW
MR Pulse Width LOW
Recovery Time MR to CP
Condition(1)
CL = 50pF
RL = 500Ω
74FCT273AT
Min.(2)
Max.
2 7.2
2 7.2
2—
1.5 —
6—
6—
2—
74FCT273CT
Min.(2)
Max.
2 5.8
2 6.1
2—
1.5 —
6—
6—
2—
Unit
ns
ns
ns
ns
ns
ns
ns
SWITCHING CHARACTERISTICS OVER OPERATING RANGE - MILITARY
Symbol
tPLH
tPHL
tPLH
tPHL
tSU
tH
tW
tW
tREM
Parameter
Propagation Delay
CP to Ox
Propagation Delay
MR to Ox
Set-up Time HIGH or LOW
Dx to CP
Hold Time HIGH or LOW
Dx to CP
CP Pulse Width HIGH or LOW
MR Pulse Width LOW
Recovery Time MR to CP
Condition(1)
CL = 50pF
RL = 500Ω
54FCT273T
Min.(2)
Max.
2 15
2 15
3.5 —
2—
7—
7—
5—
54FCT273AT
Min.(2)
Max.
2 8.3
2 8.3
2—
1.5 —
6—
6—
2.5 —
54FCT273CT
Min.(2)
Max.
2 6.5
2 6.8
2—
1.5 —
6—
6—
2.5 —
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
Unit
ns
ns
ns
ns
ns
ns
ns
5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet IDT54FCT273T.PDF ] | |
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